16

Am28F256A

Toggle Bit—DQ6

The device also features a “Toggle Bit” as a method to

indicate to the host system that the Embedded algo-

rithms are either in progress or completed.

Successive attempts to read data from the device at a

valid address, while the Embedded Program algorithm

is in progress, or at any address while the Embedded

Erase algorithm is in progress, will result in DQ6 tog-

gling between one and zero. Once the Embedded Pro-

gram or Erase algorithm is completed, DQ6 will stop

toggling to indicate the completion of either Embedded

operation. Only on the next read cycle will valid data be

obtained. The toggle bit is valid after the rising edge of

the first WE# pulse of the two write pulse sequence, un-

like Data# Polling which is valid after the rising edge of

the second WE# pulse. This feature allows the user to

determine if the device is partially through the two write

pulse sequence.

See Figures 5 and 6 for the Toggle Bit timing specifica-

tions and diagrams.

START

Fail

No

DQ6 = Toggle

?

DQ5 = 1

?

Pass

Yes

No

Read Byte

(DQ0–DQ7)

Addr = VA

Read Byte

(DQ0–DQ7)

Addr = VA

Yes

No

Yes

DQ6 = Toggle

?

VA = Byte address for programming

= XXXXh during chip erase

18879C-10

Note:

DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.

Figure 5.

Toggle Bit Algorithm