AM79C90PC datasheet(23/62 Pages) AMD

23 / 62 page

P R E L I M I N A R Y

AMD

Am79C90

Control and Status Register 3 (CSR3)

CSR3 allows redefinition of the Bus Master interface.

READ/WRITE:

Accessible only when the STOP bit

of CSR

0 is ONE and RAP = 11.

CSR

3 is cleared by RESET or by

setting the STOP bit in CSR

2 1

BCON

ACON

BSWP

RES

17881B-18

Bit

Name

Description

15:03

RES

Reserved. Read as zeroes. Write as

zeroes.

BSWP

BYTE SWAP allows the chip to oper-

ate in systems that consider bits

(15:08) of data to be pointed at an

even address and bits (07:00) to be

pointed at an odd address.

When BSWP = 1, the C-LANCE will

swap the high and low bytes on DMA

data transfers between the Receive

FIFO and bus memory. Only data

from the Receive FIFO transfers is

swapped; the Initialization Block

data and the Descriptor Ring entries

are NOT swapped.

BSWP is READ/WRITE and cleared

RESET or by setting the STOP bit

in CSR

ACON

ALE CONTROL defines the asser-

tive state of ALE when the C-LANCE

is a Bus Master. ACON is READ/

WRITE and cleared by

RESET and

by setting the STOP bit in CSR

ACON

ALE

Asserted HIGH

Asserted LOW

BCON

BYTE CONTROL redefines the Byte

Mask and Hold l/O pins. BCON is

READ/WRITE

and

cleared

RESET or by setting the STOP bit in

CSR

BCON

Pin 16

Pin 15 Pin 17

BM1

BM0

HOLD

BUSAKO BYTE BUSRQ

All data transfers from the C-LANCE in the Bus Master

mode are in words. However, the C-LANCE can handle

odd address boundaries and/or packets with an odd

number of bytes.

Initialization

Initialization Block

Chip initialization includes the reading of the initializa-

tion block in memory to obtain the operating parame-

ters. The following is a definition of the Initialization

Block.

The Initialization Block is read by the C-LANCE when

the INIT bit in CSR0 is set. The INIT bit should be set be-

fore or concurrent with the STRT bit to insure proper pa-

rameter initialization and chip operation. After the

C-LANCE has read the Initialization Block, IDON is set

in CSR0 and an interrupt is generated if INEA = 1.

Higher Address

TLEN–TDR (23:16)

IADR +22

TDRA (15:00)

IADR +20

RLEN–RDRA (23:16) IADR +18

RDRA (15:00)

IADR +16

LADRF (63:48)

IADR +14

LADRF (47:32)

IADR +12

LADRF (31:16)

IADR +10

LADRF (15:00)

IADR +08

PADR (47:32)

IADR +06

PADR (31:16)

IADR +04

PADR (15:00)

IADR +02

Base Address of Block MODE

IADR +00

Mode

The Mode Register allows alteration of the C-LANCE’s

operating parameters. Normal operation is with the

Mode Register clear.

DRX

DTX

LOOP

DTCR

COLL

DRTY

INTL

2 1

6 5

RES

PROM

17881B-19

EMBA

AM79C90PC Datasheet(PDF) 23 Page - Advanced Micro Devices

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