AM79C90PC datasheet(27/62 Pages) AMD

27 / 62 page

P R E L I M I N A R Y

AMD

Am79C90

Buffer Management

Buffer Management is accomplished through message

descriptors organized in ring structures in memory.

Each message descriptor entry is four words long.

There are two rings allocated for the device: a Receive

ring and a Transmit ring. The device is capable of polling

each ring for buffers to either empty or fill with packets to

or from the channel. The device is also capable of enter-

ing status information in the descriptor entry. C-LANCE

polling is limited to looking one ahead of the descriptor

entry the C-LANCE is currently working with.

The location of the descriptor rings and their length are

found in the initialization block, accessed during the in-

itialization procedure by the C-LANCE. Writing a “ONE”

into the STRT bit of CSR0 will cause the C-LANCE to

start accessing the descriptor rings and enable it to send

and receive packets.

The C-LANCE communicates with a HOST device

through the ring structures in memory. Each entry in the

ring is either owned by the C-LANCE or the HOST.

There is an ownership bit (OWN) in the message de-

scriptor entry. Mutual exclusion is accomplished by a

protocol which states that each device can only relin-

quish ownership of the descriptor entry to the other de-

vice; it can never take ownership, and no device can

change the state of any field in any entry after it has relin-

quished ownership.

Descriptor Ring

Each descriptor in a ring in memory is a 4-word entry.

The following is the format of the receive and the trans-

mit descriptors.

Receive Message Descriptor Entry

Receive Message Descriptor 0 (RMD0)

17881B-25

LADR

Bit

Name

Description

15:00

LADR

The LOW ORDER 16 address bits of

the buffer pointed to by this descrip-

tor. LADR is written by the host and is

not changed by the C-LANCE.

Receive Message Descriptor 1 (RMD1)

ENP

STP

BUFF

CRC

OFLO

FRAM

ERR

OWN

8 7

HADR

17881B-26

Bit

Name

Description

OWN

This bit indicates that the descriptor

entry is owned by the host (OWN = 0)

or by the C-LANCE (OWN = 1). The

C-LANCE clears the OWN bit after

filling the buffer pointed to by the de-

scriptor entry. The host sets the

OWN bit after emptying the buffer.

Once the C-LANCE or host has relin-

quished ownership of a buffer, it

must not change any field in the four

words that comprise the descriptor

entry.

ERR

ERROR summary is the OR of

FRAM, OFLO, CRC or BUFF.

FRAM

FRAMING ERROR indicates that

the incoming packet contained a

non-integer multiple of eight bits and

there was a CRC error. If there was

not a CRC error on the incoming

packet, then FRAM will not be set

even if there was a non-integer multi-

ple of eight bits in the packet. FRAM

is not valid in internal loopback

mode. FRAM is valid only when ENP

is set and OFLO is not.

AM79C90PC Datasheet(PDF) 27 Page - Advanced Micro Devices

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