AM79C989JC datasheet(27/37 Pages) AMD

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Am79C989

PRELIMINARY

Status Register (Reg 19)

The Status Register (Reg 19) contains Read/Only (R/

O) and Cleared on Read (COR) bits which indicate

status beyond the Auto-Negotiation status registers.

This register is duplicated for each port.

Error Mask Register (Reg 20)

The Error Mask Register (Reg 20) determines which

errors will be reported in the Summary Register (Reg

16). The Error Mask Register contains Read/Write

(R/W) or Read/Only (R/O) bits. If an error does occur

and the Mask enable bit is set the Error bit in the Sum-

mary Register (Reg 17) will not be asserted. This reg-

ister is duplicated for each port.

Table 19.

Error Mask Register (Reg 20)

Bit(s)

Name

Description

Read/

Write

Default/

Reset

15:3

Reserved

Written and read as zero.

R/O

Rate Mismatch

Error

1 = Frames received underﬂowed or overﬂowed the elasticity FIFO;

0 = No rate mismatch has occurred.

R/O, COR

Receive Polarity

Reversed

1 = Receive polarity of the 10BASE-T receivers is reversed;

0 = Receive polarity is correct.

R/O

Jabber Error

1 = 10BASE-T transmit circuit is in the Jabber state;

0 = 10BASE-T transmit circuit not in the Jabber state.

This bit is automatically cleared when the jabber condition

terminates.

R/O

Bit(s)

Name

Description

Read/

Write

Default/

Reset

15:3

Reserved

Written and read as zero.

R/O

Rate Mismatch

Error Enabled

1 = Rate Mismatch Error reportable in the Summary Register;

0 = Rate Mismatch Error not reportable in the Summary Register.

R/W

Receive Polarity

Reversed Error

Enable

1 = Receive Polarity Reversed reportable in the Summary Register

as an Error;

0 = Receive Polarity Reversed bit not reportable as an error in the

Summary Register.

R/W

Jabber Error

Enable

1 = Jabber error reportable in the Summary Register;

0 = Jabber error not reportable in the Summary Register.

R/W

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