AM79C989JC datasheet(11/37 Pages) AMD

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Am79C989

PRELIMINARY

RXD3

10BASE-T Receive Data Port 3

Input

RXD3

± are the 10BASE-T differential data receivers for

port 3.

AUI Signal Pins

AUI Data Out

Output

When Port 0 is conﬁgured for AUI, DO

± are the AUI dif-

ferential data out drivers. Data is transmitted with

Manchester encoded signaling compliant with IEEE

802.3 standards.

AUI Data In

Input

When Port 0 is conﬁgured for AUI (Control Register

Reg 18 bit 2), DI

± are the AUI differential data in receiv-

ers. Data is indicated by Manchester encoded signal-

ing compliant with IEEE 802.3 standards.

PCI/CI+

Pseudo-AUI Collision, AUI Collision Int (-)

Input/Input

When Interrupt Enable is true (Control Register Reg 18

bit 5) and port 0 is conﬁgured for AUI (Control Register

Reg 18 bit 2), this pin is conﬁgured as PCI. PCI is a sin-

gle-ended pseudo-AUI collision in signal. Collision is in-

dicated by a 10 MHz pattern.

When Interrupt Enable is false (Control Register Reg

18 bit 5) and port 0 is conﬁgured for AUI (Control Reg-

ister Reg 18 bit 2), this pin is conﬁgured as CI+. CI

± are

the AUI differential collision in signals. Collision is indi-

cated by a 10 MHz pattern compliant with IEEE 802.3

standards.

QINT/CI-

QuEST Interrupt, AUI Collision Int (-)

Output/Input

When Interrupt Enable is true (Control Register Reg.

18 bit 5), this pin is conﬁgured as QINT. QINT is an ac-

tive-low signal which indicates that one of the following

conditions has occurred: Link Status Change, Duplex

Mode Change, Auto-Negotiation Change, MAU Error.

Interrupt status ﬂags and enables for individual condi-

tions are reported in the Interrupt Status and Enable

When Interrupt Enable is false (Control Register Reg

18 bit 5) and port 0 is conﬁgured for AUI (Control Reg-

ister Reg 18 bit 2), this pin is conﬁgured as CI-. CI

± are

the AUI differential collision in signals. Collision is indi-

cated by a 10-MHz pattern compliant with IEEE 802.3

standards.

QuASI Interface

QTX_EN

Multiplexed Transmit Enable

Input

QTX_EN indicates to QuEST that valid transmit data is

on QTX_DATA. QTX_EN for all 4 ports is time-division

multiplexed onto this signal and is sampled with re-

spect to SCLK. The channel’s slot is synchronized to

the rising edge of QRST/STRB.

QTX_DATA

Multiplexed Transmit Data

Input

QTX_DATA indicates serial NRZ transmit data.

QTX_DATA for all 4 ports is time-division multiplexed

onto this signal and is sampled with respect to SCLK.

The channel’s slot is synchronized to the rising edge of

QRST/STRB.

QRX_CRS

Multiplexed Receive Carrier Sense

Output

QRX_CRS indicates receive or transmit activity on the

network. QRX_CRS for all 4 ports is time-division mul-

tiplexed onto this signal and is sampled with respect to

SCLK. The channel’s slot is synchronized to the rising

edge of QRST/STRB.

QRX_VALID

Multiplexed Receive Data Valid

Output

QRX_VALID indicates that valid receive data is on

QRX_DATA. QRX_VALID for all 4 ports is time-division

multiplexed onto this signal and is sampled with re-

spect to SCLK. The channel’s slot is synchronized to

the rising edge of QRST/STRB. At the rising edge of re-

set, QRX_VALID is sampled to determine PHYAD 3.

QRX_DATA

Multiplexed Receive Data

Output

QRX_DATA indicates ser ial NRZ receive data.

QRX_DATA for all 4 ports is time-division multiplexed

onto this signal and is sampled with respect to SCLK.

The channel’s slot is synchronized to the rising edge of

QRST/STRB. At the rising edge of reset, QRX_DATA is

sampled to determine PHYAD 4.

QCLSN

Multiplexed Collision

Output

QCLSN indicates a collision condition on the network.

QCLSN for all 4 ports is time-division multiplexed onto

this signal and is sampled with respect to SCLK. The

channel’s slot is synchronized to the rising edge of

QRST/STRB. At the rising edge of reset, QCLSN is

sampled to determine PHYAD 2.

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