MACH211SP-7VC datasheet(31/37 Pages) AMD

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MACH211SP-7/10/12/15/20

POWER-UP RESET

The MACH devices have been designed with the capa-

bility to reset during system power-up. Following

power-up, all ﬂip-ﬂops will be reset to LOW. The output

state will depend on the logic polarity. This feature pro-

vides extra ﬂexibility to the designer and is especially

valuable in simplifying state machine initialization. A

timing diagram and parameter table are shown below.

Due to the synchronous operation of the power-up

reset and the wide range of ways VCC can rise to its

steady state, two conditions are required to insure a

valid power-up reset. These conditions are:

1. The VCC rise must be monotonic.

2. Following reset, the clock input must not be driven

from LOW to HIGH until all applicable input and

feedback setup times are met.

Parameter Symbol

Parameter Descriptions

Max

Unit

tPR

Power-Up Reset Time

µs

Input or Feedback Setup Time

See Switching Characteristics

tWL

Clock Width LOW

20405B-23

Power-Up Reset Waveform

tPR

tWL

4 V

VCC

Power

Registered

Output

Clock

MACH211SP-7VC Datasheet(PDF) 31 Page - Advanced Micro Devices