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28F256 Datasheet(PDF) 25 Page - Advanced Micro Devices

Part # 28F256
Description  256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
PDF  35 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

28F256 Datasheet(HTML) 25 Page - Advanced Micro Devices

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Am28F256A
25
AC Characteristics—Write/Erase/Program Operations
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Embedded program operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the
minimum time for one pass through the programming algorithm.
3. Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and 1 sec array erase time. This is a typical
time for one embedded erase operation.
4. Not 100% tested.
Parameter Symbols
Parameter Description
Am28F256A Speed Options
Unit
JEDEC
Standard
-70
-90
-120
-150
-200
tAVAV
tWC
Write Cycle Time (Note 4)
Min
70
90
120
150
200
ns
tAVWL
tAS
Address Setup Time
Min
0000
0
ns
tWLAX
tAH
Address Hold Time
Min
45
45
50
60
75
ns
tDVWH
tDS
Data Setup Time
Min
45
45
50
50
50
ns
tWHDX
tDH
Data Hold Time
Min
10
10
10
10
10
ns
tOEH
Output Enable Hold Time for
Embedded Algorithm only
Min
10
10
10
10
10
ns
tGHWL
Read Recovery Time before Write
Min
0000
0
µs
tELWLE
tCSE
Chip Enable Embedded Algorithm
Setup Time
Min
20
20
20
20
20
ns
tWHEH
tCH
Chip Enable Hold Time
Min
0000
0
ns
tWLWH
tWP
Write Pulse Width
Min
45
45
50
60
60
ns
tWHWL
tWPH
Write Pulse Width HIGH
Min
20
20
20
20
20
ns
tWHWH3
Embedded Programming Operation
(Note 2)
Min
14
14
14
14
14
µs
tWHWH4
Embedded Erase Operation (Note 3)
Typ
5555
5
sec
tVPEL
VPP Setup Time to Chip Enable LOW
(Note 4)
Min
100
100
100
100
100
ns
tVCS
VCC Setup Time to Chip Enable LOW
(Note 4)
Min
50
50
50
50
50
µs
tVPPR
VPP Rise Time 90% VPPH (Note 4)
Min
500
500
500
500
500
ns
tVPPF
VPP Fall Time 90% VPPL (Note 4)
Min
500
500
500
500
500
ns
tLKO
VCC < VLKO to Reset (Note 4)
Min
100
100
100
100
100
ns



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