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28F256 Datasheet(PDF) 29 Page - Advanced Micro Devices

Part # 28F256
Description  256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
PDF  35 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

28F256 Datasheet(HTML) 29 Page - Advanced Micro Devices

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Am28F256A
29
AC CHARACTERISTICS—WRITE/ERASE/PROGRAM OPERATIONS
Alternate CE# Controlled Writes
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Embedded program operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the
minimum time for one pass through the programming algorithm.
3. Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a
typical time for one embedded erase operation.
4. Not 100% tested.
Parameter Symbols
Parameter Description
Am28F256A Speed Options
Unit
JEDEC
Standard
-70
-90
-120
-150
-200
tAVAV
tWC
Write Cycle Time (Note 4)
Min
70
90
120
150
200
ns
tAVEL
tAS
Address Setup Time
Min
0
0
0
0
0
ns
tELAX
tAH
Address Hold Time
Min
45
45
50
60
75
ns
tDVEH
tDS
Data Setup Time
Min
45
45
50
50
50
ns
tEHDX
tg
Data Hold Time
Min
10
10
10
10
10
ns
tOEH
Output Enable Hold Time for
Embedded Algorithm only
Min
10
101010
10
ns
tGHEL
Read Recovery Time Before Write
Min
0
0
0
0
0
µs
tWLEL
tWS
WE
# Setup Time by CE#
Min
0
0
000
ns
tEHWK
tWH
WE
# Hold Time
Min
0
0
0
0
0
ns
tELEH
tCP
Write Pulse Width
Min
65
65
70
80
80
ns
tEHEL
tCPH
Write Pulse Width HIGH
Min
20
20
20
20
20
ns
tEHEH3
Embedded Programming Operation
(Note 2)
Min
14
141414
14
µs
tEHEH4
Embedded Erase Operation (Note 3)
Typ
5
5
5
5
5
sec
tVPEL
VPP Setup Time to Chip Enable LOW
(Note 4)
Min
100
100
100
100
100
ns
tVCS
VCC Setup Time to Chip Enable LOW
(Note 4)
Min
50
505050
50
µs
tVPPR
VPP Rise Time 90% VPPH (Note 4)
Min
500
500
500
500
500
ns
tVPPF
VPP Fall Time 90% VPPL (Note 4)
Min
500
500
500
500
500
ns
tLKO
VCC < VLKO to Reset (Note 4)
Min
100
100
100
100
100
ns



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