TAS5076PFC datasheet(13/64 Pages) TI

13 / 64 page

Architecture Overview

SLES090A—November 2003—Revised January 2004

TAS5076

If the master clock input can encounter high clock or low clock period of less than 20 ns while the data rates

are changing, then RESET must be applied during this time. There are two recommended control procedures

for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These

control sequences are shown in Section 4.

Table 2−1. Normal-Speed, Double-Speed, and Quad-Speed Operation

QUAD-SPEED CONTROL

DBSPD TERMINAL OR

CONTROL REGISTER BIT

MODE

SPEED SELECTION

Master or slave

Normal speed

Master or slave

Double speed

Master or slave

Quad speed

Slave

Quad speed if MCLK_IN = 128Fs

Master or slave

Error

2.1.2 Clock Master/Slave Mode (M_S)

Clock master and slave mode can be invoked using the M_S (master slave) terminal.

This terminal specifies the default mode that is set immediately following a device RESET. The serial data

interface setting permits the clock generation mode to be changed during normal operation.

The transition to master mode occurs following a RESET when M_S terminal has a logic high applied.

The transition to slave mode occurs following a RESET when M_S terminal has a logic low applied.

2.1.3 Clock Master Mode

When M_S = 1 following a RESET, the TAS5076 provides the master clock, SCLK, and LRCLK to the rest of

the system. In the master mode, the TAS5076 outputs the audio system clocks MCLK_OUT, SCLK, and

LRCLK.

The TAS5076 device generates these clocks plus its internal clocks from the internal phase-locked loop (PLL).

The reference clock for the PLL can be provided by either an external clock source (attached to XTAL_IN) or

a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached to MCLK_IN

is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample

rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK

frequency is the data sample rate.

TAS5076PFC Datasheet(PDF) 13 Page - Texas Instruments