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LMZ10501SH Datasheet(PDF) 14 Page - Texas Instruments |
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LMZ10501SH Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 25 page ![]() 1V/Div 20 MHz BW 5 µs/Div SWITCH NODE INPUT VOLTAGE 1V/Div 100 µs/Div 1V/Div 1V/Div 0.5A/Div 100 mA/Div VCON IL IIN VOUT LMZ10501 SNVS677D – MAY 2011 – REVISED MARCH 2013 www.ti.com Figure 36. Hiccup behavior with persistent output short circuit. Since the output current is limited during normal startup by the softstart function, the current charging the output capacitor is also limited. This results in a smooth VOUT ramp up to nominal voltage. However, using excessively large output capacitance or VCON capacitance under normal conditions can prevent the output voltage from reaching 0.375V at the end of the startup sequence. In such cases the module will maintain the described above hiccup mode and the output voltage will not ramp up to final value. To cause this condition, one would have to use unnecessarily large output capacitance for 1A load applications. See the INPUT AND OUTPUT CAPACITOR SELECTION section for guidance on maximum capacitances for different output voltage settings. HIGH DUTY CYCLE OPERATION The LMZ10501 features a transition mode designed to extend the output regulation range to the minimum possible input voltage. As the input voltage decreases closer and closer to VOUT, the off-time of the PFET gets smaller and smaller and the duty cycle eventually needs to reach 100% to support the output voltage. The input voltage at which the duty cycle reaches 100% is the edge of regulation. When the LMZ10501 input voltage is lowered, such that the off-time of the PFET reduces to less than 35ns, the LMZ10501 doubles the switching period to extend the off-time for that VIN and maintain regulation. If VIN is lowered even more, the off-time of the PFET will reach the 35ns mark again. The LMZ10501 will then reduce the frequency again, achieving less than 100% duty cycle operation and maintaining regulation. As VIN is lowered even more, the LMZ10501 will continue to scale down the frequency, aiming to maintain at least 35ns off time. Eventually, as the input voltage decreases further, 100% duty cycle is reached. This behavior of extending the VIN regulation range is illustrated in the following plot. Figure 37. High duty cycle operation and switching frequency reduction. 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LMZ10501 |
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