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LMZ10501SH Datasheet(PDF) 18 Page - Texas Instruments

Part # LMZ10501SH
Description  LMZ10501 1A SIMPLE SWITCHER Nano Module with 5.5V Maximum Input Voltage
PDF  25 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMZ10501SH Datasheet(HTML) 18 Page - Texas Instruments

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INPUT
CAPACITOR
OUTPUT
CAPACITOR
FEEDBACK
TRACE
VIN
VOUT
VCON
CAPACITOR
VREF
VIN
PGND
VOUT
SGND
FB
SGND CONNECTION TO
QUIET PGND PLANE
VCON
EN
RT
RESISTOR
RB
RESISTOR
HIGH di/dt LOOP
KEEP IT SMALL
PGND
LMZ10501
SNVS677D – MAY 2011 – REVISED MARCH 2013
www.ti.com
Board Layout Considerations
Figure 39. Example Top Layer Board Layout
The board layout of any DC-DC switching converter is critical for the optimal performance of the design. Bad
PCB layout design can disrupt the operation of an otherwise good schematic design. Even if the regulator still
converts the voltage properly, the board layout can mean the difference between passing or failing EMI
regulations. In a Buck converter, the most critical board layout path is between the input capacitor ground
terminal and the synchronous rectifier ground. The loop formed by the input capacitor and the power FETs is a
path for the high di/dt switching current during each switching period. This loop should always be kept as short
as possible when laying out a board for any Buck converter.
The LMZ10501 integrates the inductor and simplifies the DC-DC converter board layout. Refer to the example
layout in Figure 39. There are a few basic requirements to achieve a good LMZ10501 layout.
1. Place the input capacitor CIN as close as possible to the VIN and PGND terminals. VIN (pin 7) and PGND
(pin 6) on the LMZ10501 are next to each other which makes the input capacitor placement simple.
2. Place the VCON filter capacitor CVC and the RB RT resistive divider as close as possible to the VCON and
SGND terminals.The CVC capacitor (not RB) should be the component closer to the VCON pin, as shown in
Figure 39. This allows for better bypass of the control voltage set at VCON.
3. Run the feedback trace (from VOUT to FB) away from noise sources.
4. Connect SGND to a quiet GND plane.
5. Provide enough PCB area for proper heatsinking. Refer to the Electrical Characteristics table for example
θJA values for different board areas. Also, refer to AN-2020 for additional thermal design hints.
Refer to the evaluation board application note AN-2166 for a complete board layout example.
18
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMZ10501



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