AS3543 datasheet(67/92 Pages) AMSCO

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Revision 1.11

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AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 60. Hibernation Register

Name

Base

Default

Hibernation

2-wire serial

00h

Offset: 17h-6

PMU Hibernation Control Register

Hibernation starts when writing this register.

This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

n/a

KEEP_PVDD2

R/W

Keeps the programmed PVDD2 level during hibernation.

0: power down PVDD2

1: keep PVDD2

KEEP_PVDD1

R/W

Keeps the programmed PVDD1 level during hibernation.

0: power down PVDD1

1: keep PVDD1

4:2

000

n/a

KEEP_CVDD2

R/W

Keeps the programmed CVDD2 level during hibernation.

0: power down CVDD2

1: keep CVDD2

KEEP_CVDD1

R/W

Keeps the programmed PVDD1 level during hibernation.

0: power down CVDD1

1: keep CVDD1

Table 61. DCDC_Cntr Register

Name

Base

Default

DCDC_Cntr

2-wire serial

00h

Offset: 17h-7

DC/DC Step Down Control Register

This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

CVDD2_fast

R/W

Selects a faster regulation mode for CVDD2 suitable for larger

load changes.

0: normal mode, Cext=10uF

1: fast mode, Cext=22uF required

CVDD1_fast

R/W

Selects a faster regulation mode for CVDD1 suitable for larger

load changes.

0: normal mode, Cext=10uF

1: fast mode, Cext=22uF required

CVDD2_freq

R/W

Selects the switching frequency for DCDC2

0: 2MHz

1: 1MHz

CVDD1_freq

R/W

Selects the switching frequency for DCDC2

0: 2MHz

1: 1MHz

AS3543 Datasheet(PDF) 67 Page - ams AG

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