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AS3543 Datasheet(PDF) 26 Page - ams AG |
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AS3543 Datasheet(HTML) 26 Page - ams AG |
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26 / 92 page  www.austriamicrosystems.com Revision 1.11 25 - 91 AS3543 3v2 Data Sheet - D e t a i l e d D e s c r i p t i o n - A u d i o F u n c t i o n s Figure 12. I2S left justified mode 8.5.6 Parameter DVDD=2.9V, TA=25°C, Slave Mode, f S=48kHz, MCLK = 128*fS, unless otherwise specified Table 15. I2S Timing Symbol Parameter Condition Min Typ Max Unit tSCLK SCLK Cycle Time 160 ns tSCLKH SCLK Pulse Width High 80 ns tSCLKL SCLK Pulse Width Low 80 ns TLRSU LRCK Setup Time before SCLK rising edge 80 ns TLRHD LRCK Hold Time after SCLK rising edge 80 ns tSDSU SDI setup time before SCLK rising edge 25 ns tSDHD SDI hold time after SCLK rising edge 25 ns tSDOD SDO Delay from SCLK falling edge 25 ns tJITTER Jitter of LRCK internal PLL generates MCLK from LRCK -20 20 ns I2S direct mode TSCD SCLK delay after MCLK rising edge 0.5 1.5 ns TLRD LRLCK delay after SCLK rising edge 0.5 1.5 ns tSDSU SDI setup time before SCLK rising edge 5 ns tSDHD SDI hold time after SCLK rising edge 5 ns tSDOD SDO Delay from SCLK falling edge 15 ns |
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