AS3543 datasheet(80/92 Pages) AMSCO

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AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 82. First Interrupt Register

Name

Base

Default

IRQENRD_0

2-wire serial

00h

Offset: 23h

First Interrupt Register

Please be aware that writing to this register will enable/disable the

corresponding interrupts, while reading gets the actual interrupt status and

will clear the register at the same time. It is not possible to read back the

interrupt enable/disable settings. This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

CVDD1_SD

Invokes shut-down of AFE when a –10% under-voltage spike

at CVDD1 occurs

0: disable

1: enable

CVDD1_under

This bit is set when a –5% under-voltage at CVDD1 occurs

CVDD1_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

CVDD1

0: disable

1: enable

CVDD1_over

This bit is set when a +8% over-voltage at CVDD1 occurs

5:4

n/a

PVDD2_SD

Invokes shut-down of AFE when a –10% under-voltage spike

at PVDD2 occurs

0: disable

1: enable

PVDD2_under

This bit is set when a –5% under-voltage at PVDD2 occurs

PVDD2_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

PVDD2

0: disable

1: enable

PVDD2_over

This bit is set when a +5% over-voltage at PVDD2 occurs

PVDD1_SD

Invokes shut-down of AFE when a –10% under-voltage spike

at PVDD1 occurs

0: disable

1: enable

PVDD1_under

This bit is set when a –5% under-voltage at PVDD1 occurs

PVDD1_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

PVDD1

0: disable

1: enable

PVDD1_over

This bit is set when a +5% over-voltage at PVDD1 occurs

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