CDC7005RGZ datasheet(16/34 Pages) TI

16 / 34 page

CDC7005

3.3V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

SCAS685L− DECEMBER 2002 − REVISED JUNE 2009

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

device characteristics over recommended operating free-air temperature range (unless otherwise

noted)(continued)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tPLH/tPHL

Propagation delay rising/falling edge

VCXO_IN to Yn

500

950

tsk(p)

LVPECL pulse skew

tsk(o)

LVPECL output skew (see Note 14)

See Figure 11, Mode 1−2−4−8−8

tsk(o)

LVPECL output skew (see Note 14)

See Figure 11, Mode 1−1−1−1−1

tr / tf

Rise and fall time

20% to 80% of VOD, See Figure 10

180

350

Input capacitance at VCXO_IN,

VCXO_IB

1.5

Phase Detector

fCPmax

Maximum charge pump frequency

PFD pulse width delay is 0 ps

100

MHz

Charge Pump

ICP

Charge pump sink/source current

range

VCP = 0.5 VCC, See Table 9

±0.625

±8

ICP3St

Charge pump 3-state current

0.5 V < VCP < VCC − 0.5 V

ICPA

ICP absolute accuracy

VCP = 0.5 VCC

20%

ICPM

Sink/source current matching

VCP = 0.5 VCC

IVCPM

ICP vs VCP matching

0.5 V < VCP < VCC − 0.5 V

10%

Operational Amplifier

Supply current

AVCC = 3.6 V

VIO

Input offset voltage

IIB

Input bias current

(| IOPA_IP | + | IOPA_IN |) / 2

IIO

Input offset current

| IOPA_IP − IOPA_IN |

Input resistance

0.5 VCC ±500 mV

Ω

VICR

Common-mode input voltage range

0.2

VCC−0.2

AOL

Open-loop voltage gain

See Figure 17, f = 1 kHz

GBW

Gain bandwidth

See Figure 14

MHz

Slew rate

See Figure 14, 20% − 80% of VO

µs

Output voltage swing

RL = 10 kΩ

0.2

VCC−0.2

Output voltage swing

RL = 2 kΩ

0.3

VCC−0.3

Output resistance

Ω

IOS

Short-circuit output current

Sourcing

−20

IOS

Short-circuit output current

Sinking

CMRR

Common-mode rejection ratio

VINPP = 500 mV and

f = 1 kHz, (see Figure 15)

PSRR

Power supply rejection ratio

AVCC modulated with sine wave

from

3 V to 3.6 V and f = 100 Hz (see

Figure 16)

Input noise voltage

f = 1 kHz, see Figure 14, VIN = 0 V

500

nV/

√Hz

† All typical values are at VCC = 3.3 V, temperature = 25°C.

NOTE 14: The tsk(o) specification is only valid for equal loading of all outputs.

CDC7005RGZ Datasheet(PDF) 16 Page - Texas Instruments

CDC7005RGZ Datasheet(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL