ATF1504AS datasheet(12/21 Pages) ATMEL

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ATF1504ASZ

Power Down Mode

The ATF1504AS includes an optional pin controlled power

down feature.When this mode is enabled, the PD pin acts

as the power down pin. When the PD pin is high, the device

supply current is reduced to less than 3 mA. During power

down, all output data and internal logic states are latched

and held. Therefore, all registered and combinatorial output

data remain valid. Any outputs which were in a Hi-Z state at

the onset will remain at Hi-Z. During power down, all input

signals except the power down pin are blocked. Input and

I/O hold latches remain active to insure that pins do not

float to indeterminate levels, further reducing system

power. The power down pin feature is enabled in the logic

design file. Designs using the power down pin may not use

the PD pin logic array input. However, all other PD pin mac-

rocell resources may still be used, including the buried

feedback and foldback product term array inputs.

Notes:

1. For slow slew outputs, add t

SSO.

2. Pin or Product Term.

JTAG-BST/ISP Overview

The JTAG boundary-scan testing is controlled by the Test

Access Port (TAP) controller in the ATF1504AS. The

boundary-scan technique involves the inclusion of a shift-

to each component so that signals at component bound-

aries can be controlled and observed using scan testing

principles. Each input pin and I/O pin has its own boundary

scan cell (BSC) in order to support boundary scan testing.

The ATF1504AS does not currently include a Test Reset

(TRST) input pin because the TAP controller is automati-

cally reset at power up. The five JTAG modes supported

in clude : SAM PLE/ PREL O AD, EXTEST , BYPASS,

IDCODE and HIGHZ. The ATF1504AS’s ISP can be fully

described using JTAG’s BSDL as described in IEEE Stan-

dard 1149.1b. This allows ATF1504AS programming to be

described and implemented using any one of the 3rd party

development tools supporting this standard.

The ATF1504AS has the option of using four JTAG-stan-

dard I/O pins for boundary scan testing (BST) and in-sys-

tem programming (ISP) purposes. The ATF1504AS is

programmable through the four JTAG pins using the IEEE

standard JTAG programming protocol established by IEEE

Standard 1149.1 using 5V TTL-level programming signals

from the ISP interface for in-system programming. The

JTAG feature is a programmable option. If JTAG (BST or

ISP) is not needed, then the four JTAG control pins are

available as I/O pins.

JTAG Boundary Scan Cell (BSC)

Testing

The ATF1504AS contains up to 68 I/O pins and 4 input

pins, depending on the device type and package type

selected. Each input pin and I/O pin has its own boundary

scan cell (BSC) in order to support boundary scan testing

as described in detail by IEEE Standard 1149.1. Typical

BSC consists of three capture registers or scan registers

and up to two update registers. There are two types of

BSCs, one for input or I/O pin, and one for the macrocells.

The BSCs in the device are chained together through the

capture registers. Input to the capture register chain is fed

in from the TDI pin while the output is directed to the TDO

pin. Capture registers are used to capture active device

data signals, to shift data in and out of the device and to

Power Down AC Characteristics(1)(2)

Symbol

Parameter

-7

-10

-15

-20

-25

Units

Min

Max

Min

MaxMin

Max

IVDH

Valid I, I/O Before PD High

GVDH

Valid OE(2) Before PD High

CVDH

Valid Clock(2) Before PD High

DHIX

I, I/O Don’t Care After PD High

DHGX

OE(2) Don’t Care After PD High

DHCX

Clock(2) Don’t Care After PD High

DLIV

PD Low to Valid I, I/O

µs

DLGV

PD Low to Valid OE (Pin or Term)

µs

DLCV

PD Low to Valid Clock (Pin or Term)

µs

DLOV

PD Low to Valid Output

µs

= Preliminary Information

ATF1504AS Datasheet(PDF) 12 Page - ATMEL Corporation

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