AT89 datasheet(13/15 Pages) ATMEL

13 / 15 page

AT89C51

4-41

Serial Port Timing: Shift Register Mode Test Conditions

(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)

Shift Register Mode Timing Waveforms

Symbol

Parameter

12 MHz Osc

Variable Oscillator

Units

Min

Max

Min

Max

tXLXL

Serial Port Clock Cycle Time

1.0

12tCLCL

µs

tQVXH

Output Data Setup to Clock Rising Edge

700

10tCLCL-133

tXHQX

Output Data Hold After Clock Rising Edge

2tCLCL-117

tXHDX

Input Data Hold After Clock Rising Edge

tXHDV

Clock Rising Edge to Input Data Valid

700

10tCLCL-133

XHDV

QVXH

XLXL

XHDX

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID

Float Waveforms(1)

Note:

For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when 100 mV change from

the loaded VOH/VOL level occurs.

LOAD

+ 0.1V

Timing Reference

Points

LOAD

- 0.1V

LOAD

+ 0.1V

- 0.1V

AC Testing Input/Output Waveforms(1)

Note:

AC Inputs during testing are driven at VCC - 0.5V for

a logic 1 and 0.45V for a logic 0. Timing measure-

ments are made at VIH min. for a logic 1 and VIL

max. for a logic 0.

0.45V

TEST POINTS

- 0.5V

0.2 V

+ 0.9V

0.2 V

- 0.1V

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