ADC083000 datasheet(39/48 Pages) TI

39 / 48 page

ADC083000

www.ti.com

SNAS358N – JUNE 2006 – REVISED JULY 2009

Manual Sample Clock Phase Adjust

The sample clock phase can be manually adjusted in the Extended Control Mode to accommodate subtle layout

differences when synchronizing multiple ADCs. Register addresses Dh and Eh provide extended mode access to

fine and coarse adjustments. Use of Low Frequency Sample Clock control, (register Eh; bit-10) is not supported

while using manual sample clock phase adjustments.

It should be noted that by just enabling the phase adjust capability (register Eh; bit-15), degradation of dynamic

performance is expected, specifically SFDR. It is intended that very small adjustments are used. Larger

increases in phase adjustments will begin to affect SNR and ultimately ENOB. Therefore, the use of coarse

phase adjustment should be minimized in favor of better system design.

Fine Clock Phase Adjust Range

Coarse Clock Phase Adjust Range

CONTROL PINS

Six control pins (without the use of the serial interface) provide a wide range of possibilities in the operation of

the ADC083000 and facilitate its use. These control pins provide Full-Scale Input Range setting, Calibration,

Calibration Delay, Output Edge Synchronization choice, LVDS Output Level choice and a Power Down feature.

Full-Scale Input Range Setting

The input full-scale range can be selected to be either 600 mVP-P or 820 mVP-P, as selected with the FSR control

input (pin 14) in the Normal Mode of operation. In the Extended Control Mode, the input full-scale range may be

set to be anywhere from 560 mVP-P to 840 mVP-P. See THE ANALOG INPUT for more information.

Calibration

The ADC083000 calibration must be run to achieve specified performance. The calibration procedure is run upon

power-up and can be run any time on command. The calibration procedure is exactly the same whether there is

an input clock present upon power up or if the clock begins some time after application of power. The CalRun

output indicator is high while a calibration is in progress. Note that the DCLK outputs are not active during a

calibration cycle, therefore it is not recommended as a system clock.

Power-On Calibration

Power-on calibration begins after a time delay following the application of power. This time delay is determined

by the setting of CalDly, as described in the Calibration Delay Section, below.

The calibration process will be not be performed if the CAL pin is high at power up. In this case, the calibration

cycle will not begin until the on-command calibration conditions are met. The ADC083000 will function with the

CAL pin held high at power up, but no calibration will be done and performance will be impaired. A manual

calibration, however, may be performed after powering up with the CAL pin high. See On-Command Calibration.

The internal power-on calibration circuitry comes up in an unknown logic state. If the input clock is not running at

power up and the power on calibration circuitry is active, it will hold the analog circuitry in power down and the

power consumption will typically be less than 25 mW. The power consumption will be normal after the clock

starts.

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ADC083000 Datasheet(PDF) 39 Page - Texas Instruments