ADC083000 datasheet(41/48 Pages) TI

41 / 48 page

ADC083000

www.ti.com

SNAS358N – JUNE 2006 – REVISED JULY 2009

For short LVDS lines and low noise systems, satisfactory performance may be realized with the OutV input low.

If the LVDS lines are long and/or the system in which the ADC083000 is used is noisy, it may be necessary to tie

the OutV pin high.

Power Down Feature

The Power Down pin (PD) allows the ADC083000 to be entirely powered down. See Power Down for details on

the power down feature.

The digital data (+/-) output pins are put into a high impedance state when the PD pin for the respective channel

is high. Upon return to normal operation, the pipeline will contain meaningless information and must be flushed.

If the PD input is brought high while a calibration is running, the device will not go into power down until the

calibration sequence is complete. However, if power is applied and PD is already high, the device will not begin

the calibration sequence until the PD input goes low. If a manual calibration is requested while the device is

powered down, the calibration will not begin at all. That is, the manual calibration input is completely ignored in

the power down state.

THE DIGITAL OUTPUTS

The ADC083000 demultiplexes the output data of each of the two ADCs on the die onto two LVDS output buses

(total of four buses, two for each ADC). For each of the two converters, the results of successive conversions

start on the falling edges of the CLK+ pin and are available on one of the two LVDS buses. The results of

conversions that start on the rising edges of the CLK+ pin are available on the other LVDS bus. This means that

the word rate at each LVDS bus is 1/2 the ADC083000 input clock rate and the two buses must be multiplexed to

obtain the entire 3 GSPS conversion result.

Since the minimum recommended input clock rate for this device is 500 MHz, the sampling rate can be reduced

to as low as 1 GSPS by using the results available on all four LVDS busses. The effective sampling rate can be

reduced to as low as 250 MSPS by decimating the data by using one bus and a 500MHz clock.

There is one LVDS output clock pair (DCLK+/-) available for use to latch the LVDS outputs on all buses. Whether

the data is sent at the rising or falling edge of DCLK is determined by the sense of the OutEdge pin, as described

in Output Edge Synchronization.

DDR (Double Data Rate) clocking can also be used. In this mode a word of data is presented with each edge of

DCLK, reducing the DCLK frequency to 1/4 the input clock frequency. When the device is in DDR mode, register

address 1h, bit 8 must be set to 0b. See the Timing Diagram section for details.

The OutV pin is used to set the LVDS differential output levels. See LVDS Output Level Control.

The output format is Offset Binary. Accordingly, a full-scale input level with VIN+ positive with respect to VIN− will

produce an output code of all ones, a full-scale input level with VIN− positive with respect to VIN+ will produce an

output code of all zeros and when VIN+ and VIN− are equal, the output code will be 128.

POWER CONSIDERATIONS

A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A

33 µF capacitor should be placed within an inch (2.5 cm) of the A/D converter power pins. A 0.1 µF capacitor

should be placed as close as possible to each VA pin, preferably within one-half centimeter. Leadless chip

capacitors are preferred because they have low lead inductance.

The VA and VDR supply pins should be isolated from each other to prevent any digital noise from being coupled

into the analog portions of the ADC. A ferrite choke, such as the JW Miller FB20009-3B, is recommended

between these supply lines when a common source is used for them.

As is the case with all high speed converters, the ADC083000 should be assumed to have little power supply

noise rejection. Any power supply used for digital circuitry in a system where a lot of digital power is being

consumed should not be used to supply power to the ADC083000. The ADC supplies should be the same supply

used for other analog circuitry, if not a dedicated supply.

Submit Documentation Feedback

Product Folder Links: ADC083000

ADC083000 Datasheet(PDF) 41 Page - Texas Instruments

ADC083000 Datasheet(HTML) 41 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL