ADC083000 datasheet(13/48 Pages) TI

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ADC083000

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SNAS358N – JUNE 2006 – REVISED JULY 2009

CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential

820mVP-P, CL = 10 pF, Differential a.c. coupled Sinewave Input Clock, fCLK = 1.5GHz at 0.5VP-P with 50% duty cycle, VBG =

Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω

Differential, after calibration. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.

(1)(2)

Units

Symbol

Parameter

Conditions

Typical(3)

Limits (3)

(Limits)

500MHz

≤ Input clock

% (min)

tCYC

Input Clock Duty Cycle

frequency

≤ 1.5 GHz (13)

% (max)

tLC

Input Clock Low Time

See(14)

333

133

ps (min)

tHC

Input Clock High Time

See(14)

333

133

ps (min)

% (min)

DCLK Duty Cycle

See(14)

% (max)

Input CLK transition to

tAD

Sampling (Aperture) Delay

1.4

Acquisition of Data

tAJ

Aperture Jitter

0.55

ps rms

Input Clock to Data Output Delay (in addition

50% of Input Clock transition

tOD

3.7

to Pipeline Delay)

to 50% of Data transition

Dd Outputs

Input

Db Outputs

Pipeline Delay (Latency) (14) (15)

Clock

Dc Outputs

13.5

Cycles

Da Outputs

14.5

AC ELECTRICAL CHARACTERISTICS - Output Clock and Data (16)

tLHT

LH Transition Time - Differential

10% to 90%

150

tHLT

HL Transition Time - Differential

10% to 90%

150

50% of DCLK transition to

50% of Data transition, SDR

tSKEWO

DCLK to Data Output Skew

±50

ps (max)

Mode

and DDR Mode, 0° DCLK (14)

tOSU

Data to DCLK Set-Up Time

DDR Mode, 90° DCLK (13)

570

tOH

DCLK to Data Hold Time

DDR Mode, 90° DCLK (13)

555

AC ELECTRICAL CHARACTERISTICS - Serial Interface Clock

fSCLK

Serial Clock Frequency

See(14)

MHz

tSS

Data to Serial Clock Setup Time

See(14)

2.5

ns (min)

tHS

Data to Serial Clock Hold Time

See(14)

ns (min)

Serial Clock Low Time

ns (min)

Serial Clock High Time

ns (min)

AC ELECTRICAL CHARACTERISTICS - General Signals

tSR

Setup Time DCLK_RST±

See(13)

tHR

Hold Time DCLK_RST±

CLK± Cyc.

tPWR

Pulse Width DCLK_RST±

See(14)

(min)

PD low to Rated Accuracy Conversion

tWU

See(14)

µs

(Wake-Up Time)

tCAL

Calibration Cycle Time

1.4 x 105

CLK± Cyc.

tCAL_L

CAL Pin Low Time

See Figure 8 (14)

(min)

(13) This parameter is specified by design and/or characterization and is not tested in production.

(14) This parameter is specified by design and is not tested in production.

(15) Each of the two converters of the ADC083000 has two LVDS output buses, which each clock data out at one quarter the sample rate.

Bus Db has a pipeline latency that is one Input Clock cycle less than the latency of bus Dd. Likewise, bus Da has a pipeline latency that

is one Input Clock cycle less than the latency of bus Dc.

(16) All parameters are measured through a transmission line and 100

Ω termination using a 0.33pF load oscilloscope probe.

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