ML9460 datasheet(2/27 Pages) ETC2

2 / 27 page

FEDL9460-01

LAPIS Semiconductor

ML9460

2/27

2. Pin Description

2.1 Pin Description

name

I/O Polarity

Descripiton

Initial

value

Handling when

not used

Attribute

Remarks

VDD

—

Logic power supply pin

—

Power

VSS

—

Logic power supply pin

—

VSS

V2L

V2R

—

Power supply pins for liquid

crystal drive level output.

Selective level.

—

Power

V2L and V2R are

connected internally with

each other.

MV2L

MV2R

—

Power supply pins for liquid

crystal drive level output.

Selective level.

—

Power

MV2L and MV2R are

connected internally with

each other.

VCL

VCR

—

Power supply pins for liquid

crystal drive level output.

Nonselective level.

—

Power

VCL and VCR are

connected internally with

each other.

YSCL



Shift clock input pin. Data

is shifted in on the falling

edge of the shift clock YSCL

of the shift register.

Low

—

CLK

I/O

—

Input-output pin for

alternating signal for liquid

crystal drive output

Low

—

Digital

See Sections 4.1.1,

“Liquid Crystal Drive

Circuit,” and 4.2.1,

“Timing of Connection

with the Segment

Driver.”

FRWS0

FRWS1

FRWS2

FRWS3

FRWS4

—

Alternating signal (FR

signal) period setting pins.

Specify the number of lines

with an integer from 2 to 31.

For operation using an

external alternating signal,

set the number of lines to 0.

Tied

High or

Low

—

Digital

See Sections 4.1.4,

“Alternating Signal

Generation Circuit.”

SEL1

SEL2

—

Liquid crystal drive output

pin switching pins

Tied

High or

Low

—

Digital

See Sections 4.1.1,

“Liquid Crystal Drive

Circuit,” and 4.1.3,

“Bidirectional Shift

DIO1

DIO2

I/O

—

Serial I/O (shift register data

input-output) pins

Tied

High or

Low

—

Digital

See Section 4.1.3,

“Bidirectional Shift

FRRES

Negative

Pin for initializing the counter

for the alternating signal

generation circuit.

Setting this pin to “L” level

sets initializes the altemating

signal(FR signal) circuit. A

“H” level FRRES is normally

used.

Low

—

Digital

DSPOF

Negative

A “L” level on this pin sets

each of the liquid crystal

drive outputs O1–O240 to

the VC level.

No internal register will be

cleared.

Low

—

Digital

DSPMS

—

Pin for selecting the method

of processing the DSPOF

signal internally

Tied

High or

Low

—

Digital

See Section 4.1.5,

“Control Circuit.”

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