FEDL9460-01

LAPIS Semiconductor

ML9460

8/27

4.2 Timing Diagram

4.2.1 Timing of Connection with the Segment Driver

Input signal FR is latched at the rise of input signal YSCL and is propagated to the liquid crystal drive circuit at

the next fall of YSCL. The DATA signal that is input from the DIO1 and DIO2 pins is latched at the fall of the

YSCL signal and propagated to the liquid crystal drive circuit. The liquid crystal drive signal level (V2, MC,

MV2) is determined by the operation between the FR signal propagated to the liquid crystal drive circuit and the

DATA signal.

When using output of the FR signal through the FR signal generation circuit, connect the FR signal to the FR pin

of the ML9461B directly. The FR signal inside of the LSI is processed by delaying it by two YSCL signals for

the FR signal output from the common driver.

Timing Diagram when the FR pin is configured as input

YSCL

DATA

D1

D2

D3

FR

M1

M2

M3

DATA

D1

D2

D3

FR

M1

M2

M3

Operation between D1 and M1

Operation between D2 and M2

Operation between D3 and M3

Timing Diagram when the FR pin is configured as output

YSCL

DATA

D1

D2

D3

FR

M1

M2

M3

DATA

D1

D2

D3

FR

M1

M2

M3

Operation between D1 and M1

Operation between D2 and M2

Operation between D3 and M3

Input signal

O1–O240 pin

outputs

Liquid crystal drive

circuit

(LSI internal signal)

Input signal

O1–O240 pin

outputs

Output signal

Liquid crystal drive

circuit

(LSI internal signal)