CS494002 datasheet(10/100 Pages) CIRRUS

10 / 100 page

1.8 Switching Characteristics — Intel® Host Slave Mode (DSPAB)

(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF)

Notes: 1. Certain timing parameters are normalized to the DSP clock period, DCLKP. DCLKP = 1/DCLK. The

DSP clock can be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns

DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code

users guide should be checked to confirm DCLK for the particular application.

Parameter

Symbol

Min

Max

Unit

Address setup before FCS and FRD low or FCS and FWR low

Tias

Address hold time after FCS and FRD low or FCS and FWR

high

Tiah

Read

Delay between FRD then FCS low or FCS then FRD low

Ticdr

Data valid after FCS and FRD low

Tidd

-21

FCS and FRD low for read

(Note 1)

Tirpw

DCLKP + 10

Data hold time after FCS or FRD high

Tidhr

Data high-Z after FCS or FRD high

Tidis

-22

FCS or FRD high to FCS and FRD low for next read (Note 1)

Tird

2*DCLKP + 10

FCS or FRD high to FCS and FWR low for next write (Note 1)

Tirdtw

2*DCLKP + 10

Write

Delay between FWR then FCS low or FCS then FWR low

Ticdw

Data setup before FCS or FWR high

Tidsu

FCS and FWR low for write

(Note 1)

Tiwpw

DCLKP + 10

Data hold after FCS or FWR high

Tidhw

FCS or FWR high to FCS and FRD low for next read (Note 1)

Tiwtrd

2*DCLKP + 10

FCS or FWR high to FCS and FWR low for next write (Note 1)

Tiwd

2*DCLKP + 10

CS494002 Datasheet(PDF) 10 Page - Cirrus Logic

CS494002 Datasheet(HTML) 10 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL