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CS494002 Datasheet(PDF) 28 Page - Cirrus Logic |
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CS494002 Datasheet(HTML) 28 Page - Cirrus Logic |
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28 / 100 page  28 1.19 Switching Characteristics — SRAM/FLASH Interface (TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF) Figure 19. SRAM/Flash Controller Timing Diagram - Write Cycle Figure 20. SRAM/Flash Controller Timing Diagram - Read Cycle Parameter Symbol Min Max Unit Write Cycle Single Byte Write Cycle Twrc (SRAM_FLASH_WR_CYCLE + 1) * DCLKP -ns Data Hold after NV_WE or NV_CS high Tdh DCLKP-5 -ns Data Valid after NV_CS and NV_WE low Tdv 10 ns Data Strobe Tds DCLKP-5 -ns Read Cycle Single Byte Read Cycle Trdc (SRAM_FLASH_RD_CYCLE + 1) * DCLKP -ns Data Strobe Tds DCLKP-5 -ns Data Hold after NV_WE or NV_CS high Tdh DCLKP+5 -ns Data Setup Time Tsu DCLKP+5 -ns XTA[19:0] NV_CS NV_WE XTD[7:0] T wrc T dh T ds T dv MSP LSP EXTA[19:0] NV_CS NV_OE EXTD[7:0] T rdc T dh T ds T su MSP LSP |
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