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W149
8
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes[3]
Input Conditions
Output Frequency
Spread %
Data Byte 0, Bit 3 = 1
CPU0:1,
SDRAM0:12 (MHz)
PCI_F, 1:5
(MHz)
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
1
1
1
100. 2
33.4
–0.5
1
1
0
(Reserved)
(Reserved)
(Reserved)
1
0
1
100
33.3
±0.5
1
0
0
103
34.3
–0.5
0
1
1
66.8
33.4
–0.5
0
1
0
83.3
41.65
–0.5
0
0
1
66.8
33.4
±0.5
0
0
0
124
41.3
–0.5
Table 7. Select Function for Data Byte 0, Bits 0:1
Function
Input Conditions
Output Conditions
Data Byte 0
CPU0:1
PCI_F,
PCI1:5
REF0:1,
IOAPIC
48MHZ
24MHZ
Bit 1
Bit 0
Normal Operation
X
0
Note 1
Note 1
14.318 MHz
48 MHz
24 MHz
Three-state
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note:
3.
CPU and PCI frequency selections are listed in Table 2 and Table 6.
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