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W163 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # W163
Description  Spread Aware?? Zero Delay Buffer
PDF  4 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

W163 Datasheet(HTML) 3 Page - Cypress Semiconductor

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W163
3
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter
Description
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TA
Operating Temperature
0 to +70
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
PD
Power Dissipation
0.5
W
DC Electrical Characteristics: TA =0°C to 70°C, VDD = 3.3V ±10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
IDD
Supply Current
Unloaded, 100 MHz
40
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
2.0
V
VOL
Output Low Voltage
IOL = 12 mA (-15)
IOL = 8 mA (-5)
0.4
V
VOH
Output High Voltage
IOL = 12 mA (-15)
IOL = 8 mA (-5)
2.4
V
IIL
Input Low Current
VIN = 0V
50
µA
IIH
Input High Current
VIN = VDD
100
µA
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
fIN
Input Frequency
10
133
MHz
fOUT
Output Frequency
15-pF load[5]
10
133
MHz
tR
Output Rise Time (-05)[1]
2.0 to 0.8V, 15-pF load
2.5
ns
Output Rise Time (-15)[1]
2.0 to 0.8V, 20-pF load
1.5
ns
tF
Output Fall Time (-05)[1]
2.0 to 0.8V, 15-pF load
2.5
ns
Output Rise Time (-15)[1]
2.0 to 0.8V, 20-pF load
1.5
ns
tICLKR
Input Clock Rise Time[1]
?ns
tICLKF
Input Clock Fall Time[1]
?ns
tPD
FBIN to REF Skew[2, 3]
Measured at VDD/2
–350
0
350
ps
tSK
Output to Output Skew
All outputs loaded equally
–250
0
250
ps
tSKDD
Device to Device Skew
Measured at FBIN pins,
VDD/2
–700
0
700
ps
tD
Duty Cycle
15-pF load[4]
45
50
55
%
tLOCK
PLL Lock Time
Power supply stable and
1.0
ms
tJC
Jitter, Cycle-to-Cycle
200
ps
Notes:
1.
Longer input rise and fall time will degrade skew and jitter performance.
2.
All AC specifications are measured with a 50
Ω transmission line, load terminated with 50Ω to 1.4V.
3.
Skew is measured at 1.4V on rising edges.
4.
Duty cycle is measured at 1.4V.
5.
For the higher drive -15, the load is 20 pF.



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