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Full Feature Peak Reducing EMI Solution
W182
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 8, 2000, rev. *A
Features
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz
≤ F
in ≤ 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Table 1. Modulation Width Selection
SS%
W182
Output
W182-5
Output
0Fin ≥ Fout ≥ Fin
– 1.25%
Fin + 0.625% ≥ Fin≥
– 0.625%
1Fin ≥ Fout ≥ Fin
– 3.75%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2
FS1
Frequency Range
00
8 MHz
≤ F
IN ≤ 10 MHz
0
1
10 MHz
≤ F
IN ≤ 15 MHz
10
15 MHz
≤ F
IN ≤ 18 MHz
11
18 MHz
≤ F
IN ≤ 28 MHz
PREMIS is a trademark of Cypress Semiconductor Corporation.
Simplified Block Diagram
Pin Configuration
SOIC
Spread Spectrum
W182
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Spread Spectrum
W182
(EMI suppressed)
3.3V or 5.0V
XTAL
X1
X2
Reference Input
Input
Output
Output
14
13
12
11
1
2
3
4
FS2
CLKIN or X1
NC or X2
GND
REFOUT
OE#
SSON#
Reset
5
6
7
8
9
10
VDD
VDD
CLKOUT
GND
SS%
FS1
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