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W216
PRELIMINARY
8
Note:
2.
CPU and PCI frequency selections are listed in Table 2 and Table 6.
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Spread On
Data Byte 0, Bit 3 = 1
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
Spread Percentage
Bit 2
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
1111
133.3
33.3 (CPU/4)
–0.5% Down
1110
124
31 (CPU/4)
–0.5% Down
1101
150
37.5 (CPU/4)
–0.5% Down
1100
140
35 (CPU/4)
–0.5% Down
1011
105
35 (CPU/3)
–0.5% Down
1010
110
36.7 (CPU/3)
–0.5% Down
1001
115
38.3 (CPU/3)
–0.5% Down
1000
120
40 (CPU/3)
–0.5% Down
0111
100
33.3 (CPU/3)
–0.5% Down
0110
Reserved
–0.5% Down
0101
112
37.3 (CPU/3)
–0.5% Down
0100
103
34.3 (CPU/3)
–0.5% Down
0011
66.8
33.4 (CPU/2)
–0.5% Down
0010
83.3
41.7 (CPU/2)
–0.5% Down
0001
75
37.5 (CPU/2)
–0.5% Down
0000
Reserved
–0.5% Down
Table 7. Select Function for Data Byte 0, Bits 0:1
Function
Input Conditions
Output Conditions
Data Byte 0
CPU_F, 1:2
PCI_F,
PCI0:5
REF0:1,
IOAPIC0,_F
48MHZ
24MHZ
Bit 1
Bit 0
Normal Operation
0
0
Note 2
Note 2
14.318 MHz
48 MHz
24 MHz
Spread Spectrum
1
0
Note 2
Note 2
14.318 MHz
48 MHz
24 MHz
Three-state
X
1
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