PRELIMINARY
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
W216
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 27, 1999, rev. **
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• Single chip system FTG for Intel® 440BX AGPset and
VIA Apollo Pro-133
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB / One 24-MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
• Seventeen SDRAM outputs provide support for 4
DIMMs
• Supports frequencies up to 150 MHz
•I2C™ interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ.
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAM0:15 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Table 1. Mode Input Table
Mode
Pin 3
0PCI_STOP#
1REF0
Table 2. Pin Selectable Frequency
Input Address
CPU_F, 1:2
(MHz)
PCI_F, 0:5
(MHz)
FS3
FS2
FS1
FS0
1111
133.3
33.3 (CPU/4)
1110
124
31 (CPU/4)
1101
150
37.5 (CPU/4)
1100
140
35 (CPU/4)
1011
105
35 (CPU/3)
1010
110
36.7 (CPU/3)
1001
115
38.3 (CPU/3)
1000
120
40 (CPU/3)
0111
100
33.3 (CPU/3)
0110
Reserved
0101
112
37.3 (CPU/3)
0100
103
34.3 (CPU/3)
0011
66.8
33.4 (CPU/2)
0010
83.3
41.7 (CPU/2)
0001
75
37.5 (CPU/2)
0000
Reserved
Block Diagram
Pin Configuration
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
[1]
VDDQ3
REF0/(PCI_STOP#)
VDDQ2
IOAPIC_F
CPU_F
CPU1
CPU2
PCI_F/MODE
XTAL
PLL Ref Freq
PLL 1
X2
X1
REF1/FS2
VDDQ3
Stop
Clock
Control
Stop
Clock
Control
PCI1
PCI2
PCI3
PCI5
48MHz/FS1
24MHz/FS0
PLL2
÷2,3,4
OSC
VDDQ2
CLK_STOP#
VDDQ3
IOAPIC0
PCI4
I2C
SDATA
Logic
SCLK
I/O Pin
Control
SDRAM0:15
SDRAMIN
16
VDDQ3
PCI0/FS3
Stop
Clock
Control
Stop
Clock
Control
SDRAM_F
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
VDDQ2
IOAPIC0
IOAPIC_F
GND
CPU_F
CPU1
VDDQ2
CPU2
GND
CLK_STOP#
SDRAM_F
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
SDRAM12
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
SDRAM14
GND
SDATA
SCLK
SDRAM13
VDDQ3
24MHz/FS0
48MHz/FS1
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