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DS1225 Datasheet(PDF) 6 Page - Dallas Semiconductor

Part # DS1225
Description  64K Nonvolatile SRAM
PDF  8 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1225 Datasheet(HTML) 6 Page - Dallas Semiconductor

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DS1225Y
021998 6/8
POWER–DOWN/POWER–UP CONDITION
3.2V
DATA RETENTION TIME
CE
VCC
tF
tPD
tR
tREC
tDR
LEAKAGE CURRENT
IL SUPPLIED FROM
LITHIUM CELL
VTP
SEE NOTE 11
POWER–DOWN/POWER–UP TIMING
PARAMETER
SYM
MIN
MAX
UNITS
NOTES
CE at VIH before Power–Down
tPD
0
µs
11
VCC Slew from VTP to 0V
tF
100
µs
VCC Slew from 0V to VTP
tR
0
µs
CE at VIH after Power–Up
tREC
2
ms
(tA = 25°C)
PARAMETER
SYM
MIN
MAX
UNITS
NOTES
Expected Data Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in a high impedance state during this period.



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