DS1867 datasheet(12/14 Pages) DALLAS

12 / 14 page

DS1867

12 of 14

102199

NOTES:

1. All voltages are referenced to ground.

2. Resistor inputs cannot exceed the substrate bias voltage, VB, in the negative direction.

3. Capacitance values apply at 25

°C.

4. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper

position. Test limits for absolute linearity are

±1.6 LSB.

5. Relative linearity is used to determine the change in voltage between successive tap positions. Test

limits for relative linearity are

±0.5 LSB.

6. Typical values are for tA =25

°C and nominal supply voltage.

7. -3 dB cutoff frequency characteristics for the DS1867 depend on potentiometer total resistance:

DS1867-010; 1 MHz, DS1867-050; 200 kHz, DS1867-100; 100 kHz.

8. COUT is active regardless of the state of RST .

9. Power-down time is specified at a minimum of 4 ms. It is the time required for the DS1867 to

guarantee wiper position storage as VCC moves from 4.5V to 3.0V.

10. This is the time from power trip-point min (3.9V) to 3.0V to guarantee wiper storage.

11. tREC is the time required before the DS1867 stored wiper position becomes valid on power-up.

12. Power trip points reference required voltage necessary for DS1867 to restore the stored wiper position

setting.

13. See Figure 11.

14. During power-up the wiper position will be set at 80H.

15. See Figure 2.

16. A device write is specified as being a controlled power-down providing enough time to complete an

EEPROM write. It is also defined as a complete bit change from one value to another, i.e., 0 to 1.

Power-downs which do not change the wiper value can be expected have 200,000-write durability.

17. Valid at 25

°C only.

DS1867 Datasheet(PDF) 12 Page - Dallas Semiconductor