DS2407 datasheet(14/31 Pages) DALLAS

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DS2407

012099 14/31

WRITE MEMORY [0Fh]

The Write Memory command is used to program the

1024–bit EPROM data field. The details of the functional

flow chart are described in the section “WRITING

EPROM MEMORY”. The data memory address range

is 0000h to 007Fh. If the bus master sends a starting

address higher than this, the nine most significant

address bits are set to zeros by the internal circuitry of

the chip. This will result in a mismatch between the CRC

calculated by the DS2407 and the CRC calculated by

the bus master, indicating an error condition.

WRITE STATUS [55h]

The Write Status command is used to program the Sta-

tus Memory field, which includes specification of pow-

er–on default settings of the Conditional Search and the

channel flip–flops as well as dynamic changes of the

Conditional Search Settings and channel flip–flops. The

details of the functional flow chart are described in the

section “WRITING EPROM MEMORY”.

The Status Memory address range is 0000h to 0007h.

The general programming algorithm is valid for the

EPROM section of the Status Memory (addresses 0 to

6) only. Status Memory Address 7 consists of SRAM

cells rather than EPROM. As a consequence, writing to

this location does not require a 12V programming pulse

and the bits 0 to 6 can be reprogrammed to any value

without limitation. Bit 7 is read–only; attempts to write to

it are ignored. The function flow for writing to status

memory location 7 is basically the same as for the

EPROM Status Memory Bytes. However, the program-

ming pulse may be, but need not be, replaced by send-

ing 8 Read Data Time Slots.

READ STATUS [AAh]

The Read Status command is used to read data from

the Status Memory field. The functional flow chart of this

command is identical to the Read Memory command.

Since the Status Memory is only 8 bytes, the DS2407

will send the 16–bit CRC after the last byte of status

information has been transmitted.

CHANNEL ACCESS [F5h]

The Channel Access command is used to access the

PIO channels to sense the logical status of the output

node and the output transistor and to change the status

of the output transistor. The bus master will follow the

command byte with two Channel Control Bytes and will

receive back the Channel Info byte.

The Channel Control bytes allow the master to select a

PIO–channel to communicate with, to specify commu-

nication parameters and to reset the activity latches.

Figure 7 shows the details. The bits CHS0 and CHS1

(Channel Control Byte 1) select the channels to commu-

nicate with. One can select one of the two channels or

both channels together.

The codes for CHS0 and CHS1 are as follows:

CHS1

CHS0

(not allowed)

channel A only

channel B only

both channels interleaved

When reading a single channel only, the logic level at the

selected PIO is sampled at the beginning of each read

time slot (Figure 9a) and immediately signaled through

the 1–Wire line. Because the PIO logic levels are

sensed at the beginning of the time slot, transitions at

the PIO during the time slot are not seen by the bus mas-

ter. When writing to a single channel, the selected PIO

will show the new status after (but not necessarily

immediately after) the 1–Wire line has returned to its idle

level of typically 5V (see Figure 9a). If the bus master

transmits a 1 (Write One Time Slot), the output transistor

of the selected channel will change its status after time

td1, which is 15

µs to 60 µs after the begin of the time

slot. If the bus master transmits a 0 (Write Zero Time

Slot), the output transistor will change its status with a

delay of td0 after the 1–Wire line has returned to its idle

level. The value of td0 may vary between 200 and 300

ns (see Figure 9a). Depending on the load conditions,

there may be additional delay until the voltage at the PIO

reaches a new logical level.

If one is communicating with both channels, the Inter-

leave Control Bit IC controls when data is sampled and

when data arrives at the PIO pins. There is an asynchro-

nous mode (IC = 0) and a synchronous mode (IC = 1).

For the asynchronous mode, both channels are

accessed in an alternating way. For the synchronous

mode, both channels are accessed simultaneously.

When reading in the asynchronous mode each channel

is sampled alternately at the start of each Read Time

Slot, beginning with channel A. The logic level detected

at the PIO is immediately transmitted to the master dur-

ing the same time slot. When reading in the synchro-

nous mode, both channels will be sampled at the same

time; the data bit from channel A will be sent to the mas-

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