DS2407 datasheet(27/31 Pages) DALLAS

27 / 31 page

DS2407

012099 27/31

When reading the data memory of the DS2407 with the

Extended Read Memory command, there are two situa-

tions where a 16–bit CRC is transmitted. One 16–bit

CRC follows each Redirection Byte, another 16–bit

CRC is received after the last byte of a memory data

page is read. The CRC at the end of the memory page is

always the result of clearing the CRC generator and

shifting in the data bytes beginning at the first addressed

memory location of the EPROM data page until the last

byte of this page. With the initial pass through the

Extended Read Memory flow chart the 16–bit CRC

value is the result of shifting the command byte into the

cleared CRC generator, followed by the two address

bytes and the Redirection Byte. Subsequent passes

through the Extended Read Memory flow chart will gen-

erate a 16–bit CRC that is the result of clearing the CRC

generator and then shifting in only the Redirection Byte.

When writing to the DS2407 (either data memory or Sta-

tus Memory), the bus master receives a 16–bit CRC to

verify that the data transfer was correct before applying

the programming pulse. With the initial pass through the

Write Memory/Status flow chart the 16–bit CRC will be

generated by clearing the CRC–generator, shifting in

the command, low address, high address and the data

byte. Subsequent passes through the Write Memory/

Status flow chart due to the DS2407 automatically incre-

menting its address counter will generate a 16–bit CRC

that is the result of loading (not shifting) the new

(incremented) address into the CRC generator and then

shifting in the new data byte.

When communicating with a PIO channel using the

Channel Access command, one can select if and how

often a 16–bit CRC will be added to the data stream.

This CRC selection is specified in the Channel Control

byte 1 and may be different every time the Channel

Access command is issued by the bus master. Depend-

ing on the CRC selection, the device can generate a

CRC after every byte that follows the Channel Info byte,

after each block of eight bytes or after each block of 32

bytes. If the CRC is enabled, with the initial pass through

the Channel Access flow chart the 16–bit CRC will be

generated by clearing the CRC–generator, shifting in

the command, Channel Control Bytes 1 and 2, Channel

Info Byte and the specified amount of data bytes (1, 8 or

32). Subsequent passes through the Channel Access

flow chart will generate a 16–bit CRC that is the result of

clearing the CRC generator and then shifting in the new

data bytes. This algorithm is valid for all accesses to the

PIO channels, continuous reading or writing as well as

toggling between read and write.

The comparison of CRC values and decision to con-

tinue with an operation are determined entirely by the

bus master. There is no circuitry on the DS2407 that pre-

vents a command sequence from proceeding if the CRC

stored in or calculated by the DS2407 does not match

the value generated by the bus master. For more details

on generating CRC values including example imple-

mentations in both hardware and software, see the

“Book of DS19xx iButton Standards”.

PROGRAM PULSE TIMING DIAGRAM Figure 16

µs

LINE TYPE LEGEND:

VPULLUP

GND

VPP

µs

480

µs

NORMAL 1–Wire

COMMUNICATION ENDS

NORMAL 1–Wire

COMMUNICATION RESUMES

Bus master active high

(12V @ 10 mA)

tRP

tFP

tDP

tDV

Resistor pull–up

tPP

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