Product Specification

SP4307

Page 8 of 10

Table 7. 5-Bit Attenuator Serial Programming

Register Map

Table 9. Parallel Interface AC Characteristics

Figure 19. Parallel Interface Timing Diagram

Table 8. Serial Interface AC Characteristics

Figure 18. Serial Interface Timing Diagram

Note: The start bit (B5) must always be low to prevent an unknown

state in the device .

Note:

programming sections of the functional pattern are clocked

at 10 MHz to verify fclk specification.

LE

Clock

Data

MSB

LSB

t

LESUP

t

SDSUP

t

SDHLD

t

LEPW

B5

B4

B3

B2

B1

B0

0C8

C4

C2

C1

C0.5

↑↑

LSB (last in

MSB (first in)

t

PDSUP

t

PDHLD

LE

t

LEPW

Parallel Data

C8:C0.5

Symbol

Parameter

Min

Max

Unit

Serial data clock

frequency (Note 1)

10

MHz

Serial clock HIGH time

30

ns

Serial clock LOW time

30

ns

LE set-up time after last

clock falling edge

10

ns

LE minimum pulse width

30

ns

Serial data set-up time

before clock rising edge

10

ns

Serial data hold time

after clock falling edge

10

ns

Symbol

Parameter

Min

Max

Unit

LE minimum pulse width

10

--

ns

Data set-up time before

rising edge of LE

10

--

ns

Data hold time after

falling edge of LE

10

--

ns

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