MA28151 datasheet(2/22 Pages) DYNEX

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MA28151

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1. FUNCTIONAL DESCRIPTION

1.1 GENERAL

The MA28151 is a Universal Synchronous/Asynchronous

Receiver/Transmitter designed for use with the MAS281

microprocessor. Like other l/O devices in a microcomputer

system, its functional configuration is programmed by the

system’s software for maximum flexibility. The MA28151 can

support most serial data techniques in use, including IBM bi-

sync.

In a communication environment, an interface device must

convert parallel format system data into serial format for

transmission, and convert incoming serial data into parallel

system data for reception. The interface device must also

delete or insert bits or characters that are functionally unique to

the communication technique. In essence, the interface should

appear transparent to the CPU for the simple input or output of

byte-oriented system data.

1.2 DATA BUS BUFFER

This 3-state, bidirectional, 8-bit buffer is used to interface

the MA28151 to the system data bus. Data is transmitted or

received by the buffer upon execution of OUTput or INput

instructions from the CPU.

Control word, Command words and Status information are

also transferred through the Data Bus Buffer. The Command

Status, Data-in and Data-out registers are separate 8-bit

registers, communicating with the system bus through the

Data Bus Buffer.

This functional block accepts inputs from the system

control bus and generates control signals for overall device

operation. It contains the Control Word Register and

Command Word Register, which store the various control

formats for the device’s functional definition.

1.3 RESET

A high on this input forces the MA28151 into idle mode.

The MA28151 will remain at idle until its functional definition is

programmed with a new set of control words. Minimum RESET

pulse width is 6 tcy (clock must be running).

The device can also be put into the idle state by a

command reset operation .

1.4 CLOCK (CLK)

The CLK input is used to generate internal device timing

and is normally connected to the clock generator (OSC) of the

system.

Please note: None of the external inputs or outputs are

referenced to CLK but the frequency of CLK must be greater

than 30 times the Receiver or Transmitter data bit rates.

1.5 DATA STROBE (DSN)

This input indicates that a data transfer is taking place.

During a CPU write operation the MA28151 reads data from

the bus on the rising edge of DSN. During a read operation the

MA28151 can output data while DSN is low. Data is valid on

the rising edge of DSN.

1.6 READ/WRITE SELECT (RDWN)

A high on the RDWN input indicates a read of data or

status information from the MA28151. A low on this input

indicates a transfer of data or control words into the MA28151.

The RDWN line is valid only when DSN is low. Figure 2

summarises the MAS28151 read/write operati ons.

1.7 CONTROL/DATA (CDN)

This input, in conjunction with the DSN and RDWN inputs,

informs the MA28151 that the word on the Data Bus is either a

data character, control word or status information.

1 = CONTROL/STATUS; 0= DATA

CDN

RDWN

DSN

CSN

ACTION

28151 TO CPU

CPU TO 28151

STATUS TO CPU

CPU TO CONTROL

BUS TRISTATE

Figure 2: Read/Write Control

1.8 CHIP SELECT (CSN)

A low on this input selects the MA28151. No reading or

writing will occur unless the device is selected. When CSN is

high, the Data Bus is in the float state and the DSN and RDWN

lines have no effect on the chip.

1.9 MODEM CONTROL

The MA28151 has a set of control inputs and outputs which

can be used to simplify the interface to almost any modem.

The modem control signals are general purpose in nature and

can be used for functions other than modem control, if

necessary.

1.10 DATA SET READY (

DSR)

The

DSR input signal is a general-purpose, 1-bit inverting

input port. Its condition can be tested by the CPU using a

Status Read operation. The

DSR input is normally used to test

modem conditions such as Data Set Ready.

1.11 DATA TERMINAL READY (

DTR)

The

DTR output signal is a general purpose, 1-bit inverting

output port. It can be set low by programming the appropriate

bit in the Command instruction word. The

DTR output signal is

normally used for modem control such as Data Terminal

Ready.

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