26

* This specification are subject to be changed without notice.

10.31.2000

EM73983

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

The basic structure of Watch-Dog-Timer control is composed by a 4-stage binary counter and a control unit .

The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the

counter will be cleared and continue counting . Otherwise, if there is a malfunction happened, the WDT control

will send a WDT signal ( low active ) to reset CPU. The WDT checking period is assign by P21 ( WDT command

port ).

0

WDT control

WDT

command port

12

3

counter clear request

RESET pin

LXIN/2

13

WDT counter

P21

mask option

tp

ts

tp=

CLK/64 (CLK=4.6MHz)

1

PROGRAM EXAMPLE:

LDIA

#1001B

; basic frequency : CLK/32, tone output

OUTA

P30

LDIA

#0111B

; volume control

OUTA

P17

LDIA

#0011B

; 1430 Hz tone output

OUTA

P24

LDIA

#0001B

OUTA

P23

WATCH-DOG-TIMER (WDT)

Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a timeup signal every

certain time . User can use the time up signal to give system a reset signal when system is fail.

This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when CPU

is reseted or in the STOP operation mode.

1

2

34

56

789

+

Random generator

Volume control register (P17)

The are 16 levels of volume for sound generator. P17 is the volume control register.

Port17

Initial value : 1111

3

2

1

0

VCR

VCR

ts/tp

1

1

1

1

15/16

1

1

1

0

14/16

::

0

0

0

1

1/16

0

0

0

0

0/16