22

* This specification are subject to be changed without notice.

EM73P461A

EM73P461A

EM73P461A

EM73P461A

EM73P461A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

12.27.2001

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

** F

** Example : LXIN=32K Hz, HIPS=01, HT=11110000B=0F0H.

⇒F

LDIA

#1111B

OUTA

P11

LDIA

#0000B

OUTA

P10

LDIA

#1001B

OUTA

P31

The value of 8-bit binary up counter can be presetted by P10 and P11. The value of registers can loaded into

the HTC when the counter starts counting or occurs overflow. If user write value to the registers before the

next overflow occurs, the preset value can be changed.

The preset value will be changed when users output the different data to P10 and P11.

The count value of HTC can be read from P10 and P11. The value is unstable when user read the value during

counting. Thus, user must disable the counter before reading the value.

The P4.0/SOUND and SOUND pins will output the squre wave in the melody mode. When the CPU is not

in the melody mode, the P4.0/SOUND is high and SOUND is low.

The P4.1/RGH pin will be the input pin in the pulse width measurement mode. User must output high to P4.1/

TRGH and then it can be the HTC external input pin. When the HTC is disabled, the P4.1 pin is a normal I/

O pin.

INTERRUPT FUNCTION

INTERRUPT FUNCTION

INTERRUPT FUNCTION

INTERRUPT FUNCTION

INTERRUPT FUNCTION

There are 6 interrupt sources, 2 external interrupt sources, 4 internal interrupt sources. Multiple

interrupts are admitted according the priority.

Type

Type

Type

Type

Type

Interrupt source

Interrupt source

Interrupt source

Interrupt source

Interrupt source

Priority

Priority

Priority

Priority

Priority

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Interrupt

Program ROM

Program ROM

Program ROM

Program ROM

Program ROM

Latch

Latch

Latch

Latch

Latch

Enable condition

Enable condition

Enable condition

Enable condition

Enable condition

entry address

entry address

entry address

entry address

entry address

External

Externalinterrupt(INT0)

1

IL5

EI=1

002H

Internal

High speed timer overflow interrupt (HTCI)

2

IL4

EI=1,MASK3=1

004H

Internal

TimerA overflow interrupt (TRGA)

3

IL3

EI=1,MASK2=1

006H

Internal

TimerB overflow interrupt (TRGB)

4

IL2

EI=1,MASK1=1

008H

Internal

Time base interrupt(TBI)

5

IL1

00AH

External

Externalinterrupt(INT1)

6

IL0

EI=1,MASK0=1

00CH

INTERRUPT STRUCTURE

INTERRUPT STRUCTURE

INTERRUPT STRUCTURE

INTERRUPT STRUCTURE

INTERRUPT STRUCTURE

Reset by system reset and program

instruction

MASK0 MASK1 MASK1 MASK2 MASK3

IL0

INT1

r0

IL1

TBI

r1

IL2

r2

IL3

TRGA

r3

IL4

r4

IL5

INT0

r5

Priority checker

EI

Entry address generator

Interrupt request

Interrupt entry address

Reset by system reset and program

instruction

Set by program instruction

TRGB

HTCI