TPS23751 datasheet(13/47 Pages) TI1

13 / 47 page

8.5

TPS23751

TPS23752

www.ti.com

SLVSB97A – JULY 2012 – REVISED AUGUST 2012

RT (Timing Resistor): A timing resistor (RT in Figure 1) connected between this pin and ARTN sets the PWM

switching frequency fSW according to Equation 1.

(1)

The switching frequency remains constant during PWM operation, but decreases as VCTL falls below VCTL_VFO.

RT is a high impedance pin. Keep the connections short and isolate them from potential noise sources.

RTN: The RTN pin provides the negative power return path for the converter. Once VDD exceeds the UVLO

threshold (VUVLO_R), the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents the RTN current from

exceeding about 140 mA until the bulk capacitance (CIN in Figure 1) is fully charged. Inrush ends and the

converter begins operating when the RTN current drops below about 125 mA. The RTN current is subsequently

limited to about 1 A. If RTN ever exceeds about 12 V, then the controller returns to inrush limiting.

RTN should be connected to ARTN for most applications.

SLPb: (TPS23752 only): The SLPb pin controls entry into Sleep Mode. A falling-edge transition applied to this

pin during normal operation initiates Sleep Mode. This mode of operation disables converter switching, increases

the current limit of the internal VC regulator, and pulls the LED output low. Cycling VDD or pulling the WAKE pin

low terminates the Sleep Mode and restores normal operation.

SRD (Synchronous Rectifier Disable): This open-drain output pulls to ARTN whenever the DC-DC converter is

enabled, inrush and soft start are complete, and the voltage at the CTL pin exceeds the threshold VCTL_VFO set

by the SRT pin. A low voltage on the SRD pin signals the synchronous rectifier to begin operation. If the CTL pin

voltage drops below VCTL_VFO, then the SRD output goes high impedance to disable the synchronous rectifier.

This action ensures that the synchronous rectifier does not operate during VFO mode.

SRT (Synchronous Rectifier Threshold): The SRT pin sets the thresholds VCTL_VFO and VCS_VFO, at which the DC-

DC converter switches between PWM and VFO. The application circuit normally uses a resistor divider

(RSRT1–RSRT2 in Figure 1) to generate a voltage of 0.5 to 1.5 V at the SRT pin. When the voltage on the CTL pin

exceeds VCTL_VFO, the converter operates in PWM mode and the SRD pin is pulled low to enable the

synchronous rectifier. When the voltage on CTL falls below VCTL_VFO, the converter operates in VFO and the

SRD pin goes high impedance to disable the synchronous rectifier. Tying SRT to ARTN disables the VFO mode.

T2P (Type-2 PSE Indicator): The controller pulls this pin to ARTN whenever type-2 hardware classification has

been observed; or the APD pin is pulled high, after the internal T2P delay is complete, and VCTL ≤ 4 V. Once T2P

is valid, VCTL has no effect on the status of T2P. The T2P output will return to a high-impedance state if the part

enters thermal shutdown, the pass MOSFET enters inrush limiting, or if a type-2 PSE was not detected and the

voltage on APD drops below its threshold. The circuitry that watches for type-2 hardware classification latches its

result when the V(VDD-VSS) voltage differential rises above the upper classification threshold. This circuit resets

when the V(VDD-VSS) voltage differential drops below the mark threshold. The T2P pin can be left unconnected if it

is not used.

VB (Bias Voltage): The VB pin is the output of an internal 5 V regulator fed from VC. A ceramic bypass capacitor

with a minimum capacitance of no less than 80 nF must connect from VB to ARTN. VB may be used to bias the

feedback optocoupler. For the TPS23752, VB may also bias pullups for SLPb and MODE.

VC (Controller Voltage): The VC pin connects to the auxiliary bias supply for the DC-DC controller. The MOSFET

gate driver draws current directly from VC. VB is regulated down from VC to provide power for the rest of the

internal control circuitry. A startup current source from VDD to VC controlled by a comparator with hysteresis

implements the converter bootstrap startup. VC must receive power from an auxiliary source, such as an auxiliary

winding on the flyback transformer, to sustain normal operation after startup. A low-ESR bypass capacitor, such

as a ceramic capacitor, must connect from VC to ARTN to supply the gate drive current required to drive the

external switching MOSFET.

The TPS23752 regulates VC to 12.8 V while in Sleep Mode to regulate the brightness of the Sleep-Mode LED.

VDD: The VDD pin connects to the positive side of the input supply. The VDD pin provides operating power to the

PD controller, allows this circuit to monitor the input line voltage, and serves as the source for DC-DC startup

current. In the TPS23752, it also supplies the LED and MPS current during Sleep-Mode operation

VSS: The VSS pin connects to the negative rail of the input supply. It serves as a local ground for the PD control

circuitry. The PowerPAD™ must connect to VSS to ensure proper operation.

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