LM25066I datasheet(21/60 Pages) TI1

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OUT

UVLO/EN

VIN

GATE

DIODE

ADR2

ADR1

ADR0

VDD

N/C

25 k:

2.1 k:

10 k:

1.3 k:

MMBT3904

OVLO

SDA

SCL

PGD

N/C

SENSE

VDD

SMBus

Interface

SMBA

RETRY

VAUX

VDD

VREF

TIMER

PWR

GND

LM25066I/IA

Auxillary ADC Input

(0V - 1.16V)

VOUT

330 PF

10 k:

0.5 m:

12V

1 PF

6.98 k:

0.47 PF

PSMN1R2-25YL

UVLO/EN

OUT

LM25066I, LM25066IA

www.ti.com

SNVS824C – JUNE 2012 – REVISED MARCH 2013

APPLICATIONS SECTION

Figure 36. Typical Application Circuit

DESIGN-IN PROCEDURE

(Refer to Figure 36 for Typical Application Circuit) Shown here is the step-by-step procedure for hardware design

of the LM25066I/A. This procedure refers to sections that provide detailed information on the following design

steps. The recommended design-in procedure is as follows:

MOSFET Selection: Determine MOSFET value based on breakdown voltage, current and power ratings.

Current Limit, RS: Determine the current limit threshold (ILIM). This threshold must be higher than the normal

maximum load current, allowing for tolerances in the current sense resistor value and the LM25066I/A Current

Limit threshold voltage. Use Equation 1 to determine the value for RS.

Power Limit Threshold: Determine the maximum allowable power dissipation for the series pass MOSFET (Q1)

using the device’s SOA information. Use Equation 2 to determine the value for RPWR.

Turn-On Time and TIMER Capacitor, CT: Determine the value for the timing capacitor at the TIMER pin (CT)

using Equation 8. The fault timeout period (tFAULT) MUST be longer than the circuit’s turn-on-time. The turn-on

time can be estimated using the equations in TURN-ON TIME, but should be verified experimentally. Review the

resulting insertion time, and the restart timing if retry is enabled.

UVLO, OVLO: Choose option A, B, C, or D from UVLO, OVLO to set the UVLO and OVLO thresholds and

hysteresis. Use the procedure for the appropriate option to determine the resistor values at the UVLO/EN and

OVLO pins.

Power Good: Choose the appropriate output voltage and calculate the required resistor divider from the output

voltage to the FB pin. Choose either VDD or OUT to connect properly sized pullup resistor for the Power Good

output (PGD).

Refer to Programming Guide section: After all hardware design is complete, refer to the programming guide

for a step by step procedure regarding software.

MOSFET SELECTION

It is recommended that the external MOSFET (Q1) selection be based on the following criteria:

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LM25066I Datasheet(PDF) 21 Page - Texas Instruments

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