LM3429 datasheet(13/50 Pages) TI1

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CSH

RCSH

LM3429

VCC

RBIAS

RMAX

VREF

RADJ

Variable Current Source

Variable

Resistance

RHSP

ILED = ICSH - IADD x

RSNS

(

)

RADJ x VREF

IADD =

RADJ + RMAX

- VBE-Q6

RBIAS

LM3429

www.ti.com

SNVS616F – APRIL 2009 – REVISED JANUARY 2010

1. External variable resistance : Adjust a potentiometer placed in series with RCSH to vary VSNS.

2. External variable current source: Source current (0 µA to ICSH) into the CSH pin to adjust VSNS.

In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading

edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.

Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming

range. Figure 6 shows how both methods are physically implemented.

Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.

However, the LEDs cannot dim completely because there is always some resistance causing signal current to

flow. This method is also susceptible to noise coupling at the CSH pin since the potentiometer increases the size

of the signal current loop.

Method 2 provides a complete dimming range and better noise performance, though it is more complex. It

consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors and a potentiometer

(RADJ), where RADJ controls the amount of current sourced into the CSH pin. A higher resistance value will source

more current into the CSH pin causing less regulated signal current through RHSP, effectively dimming the LEDs.

VREF should be a precise external voltage reference, while Q7 and Q8 should be a dual pair PNP for best

matching and performance. The additional current (IADD) sourced into the CSH pin can be calculated:

(10)

The corresponding ILED for a specific IADD is:

(11)

Figure 6. Analog Dimming Circuitry

CURRENT SENSE/CURRENT LIMIT

The LM3429 achieves peak current mode control using a comparator that monitors the MosFET transistor

current, comparing it with the COMP pin voltage as shown in Figure 7. Further, it incorporates a cycle-by-cycle

over-current protection function. Current limit is accomplished by a redundant internal current sense comparator.

If the voltage at the current sense comparator input (IS) exceeds 245 mV (typical), the on cycle is immediately

terminated. The IS input pin has an internal N-channel MosFET which pulls it down at the conclusion of every

cycle. The discharge device remains on an additional 250 ns (typical) after the beginning of a new cycle to blank

the leading edge spike on the current sense signal. The leading edge blanking (LEB) determines the minimum

achievable on-time (tON-MIN).

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