MB86604LPFV datasheet(23/56 Pages) FUJITSU

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MB86604L

(5) DMA interface

The DMA access timing described in this section is not applicable in the following cases.

During SCSI input, when the data buffer is EMPTY or when one byte is stored

During SCSI output, when the data buffer is FULL or when 31 bytes are stored

When a parity error is detected (target)

When an error which pauses the transfer occurs at the SCSI interface

• 80 series handshake mode

(a) Write timing

* : The position number indicates the position in the waveform.

Parameter

Symbol

Value

Unit

Base signal

Position*

Min.

Max.

DACK “L” assert time

DREQ “H”

tRQAK

—

DREQ “L” negate time

DACK “L”

tAKRQ

—

DREQ “H” assert time (8 bit)

DACK “H”

tAKRQ1

—

DREQ “H” assert time (16 bit)

DACK “H”

tAKRQ2

C—

2 tCLK + 40

IOWR “L” assert time

DACK “L”

tAKWR

D0—

DMBHE, DMA0 set up time

IOWR “L”

tsuDA

E20

—

DMBHE, DMA0 hold time

IOWR “H”

thDA

F20

—

IOWR “L” level pulse width

—

twWRL

G40

—

DACK “H” negate time

IOWR “L”

tWRAK1

H1 tCLK

—ns

IOWR “H”

tWRAK2

—

Input data set up time

IOWR “H”

tsuDMD

J30

—

Input data hold time

IOWR “H”

thDMD

—

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