MB91121 datasheet(8/97 Pages) FUJITSU

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MB91121

DACK1/PE5

[DACK1] DMAC external transfer request acknowledge output

(ch1) . This function is enabled with the DMAC transfer request ac-

knowledge output flag set to “Enabled”.

[PE5] General-purpose I/O port. This function is enabled with the

DMAC transfer request acknowledge output flag or DACK0 output

flag set to “Disabled”.

EOP1/PE6

[EOP1] DMAC EOP output (ch1) . This function is enabled with

the EOP output flag set to “Enabled”.

[PE6] General-purpose I/O port

DREQ2/PE7

[DREQ2] DMA external transfer request input (ch2) . Since this

input is used whenever the DMA external transfer request has

been selected as a DMA transfer trigger event, the output by the

other function must remain off unless used intentionally.

[PE7] General-purpose I/O port

DACK2/PI0

[DACK2] DMAC external transfer request acknowledge output

(ch2) . This function is enabled with the DMAC transfer request ac-

knowledge output flag set to “Enabled”.

[PI0] General-purpose I/O port. This function is enabled with the

DMAC transfer request acknowledge output flag or DACK0 output

flag set to "Disabled".

EOP2/ATG/PI1

[EOP2] DMAC EOP output (ch2) . This function is enabled with

the EOP output flag set to “Enabled”.

[ATG] A/D converter external trigger input. Since this input is used

whenever the A/D converter external trigger signal has been se-

lected as an A/D trigger event, the output by the other function

must remain off unless used intentionally.

[PI1] General-purpose I/O port. This function is enabled with the

DMAC transfer termination signal output flag set to “Disabled”.

Clock (oscillation) output.

Clock (oscillation) input.

RAS0/PB0

CSOL/PB1

CSOH/PB2

DW0/PB3

RAS1/PB4

RAS output of DRAM bank 0

CASL output of DRAM bank 0

CASH output of DRAM bank 0

WE output of DRAM bank 0 (Low active)

RAS output of DRAM bank 1

[PB0 to PB3] Can serve as a port when not used for signal output.

CS1L/PB5

CS1H/PB6

DW1/PB7

CASL output of DRAM bank 1

CASH output of DRAM bank 1

WE output of DRAM bank 1 (Low active)

[PB5 to PB7] Can serve as a port when not used for signal output.

CS0

Chip select 0 output (Low active) .

(Continued)

Pin no.

Pin name

Circuit type

Function

(Continued)

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