ADCS7476, ADCS7477, ADCS7478

SNAS192F – APRIL 2003 – REVISED MARCH 2013

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Figure 33. Entering Normal Mode

EXITING SHUTDOWN MODE

To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADCS7476/77/78 will begin powering up.

Power up typically takes 1 µs. This microsecond of power-up delay results in the first conversion result being

unusable. The second conversion performed after power-up, however, is valid, as shown in Figure 33.

If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is

done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and

remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADCS7476/77/78 will

be fully powered-up after 16 SCLK cycles.

POWER-UP TIMING

normal mode from shutdown mode. This corresponds to one "dummy" conversion for any SCLK frequency within

the specifications in this document. After this first dummy conversion, the ADCS7476/77/78 will perform

second valid conversion.

STARTUP MODE

shutdown. As such, one dummy conversion should be performed after start-up, exactly as described in POWER-

UP TIMING. The part may then be placed into either normal mode or the shutdown mode, as described in

NORMAL MODE and SHUTDOWN MODE.

POWER CONSIDERATIONS

There are three concerns relating to the power supply of these products: the effects of Power Supply Noise upon

the conversion process, the Digital Output Effect Upon Noise upon the conversion process and Power

Management of the product.

Power Supply Noise

Since the reference voltage of the ADCS7476/77/78 is the reference voltage, any noise greater than 1/2 LSB in

amplitude will have some effect upon the converter noise performance. This effect is proportional to the input

voltage level. The power supply should receive all the considerations of a reference voltage as far as stability

and noise is concerned. Using the same supply voltage for these devices as is used for digital components will

lead to degraded noise performance.

Digital Output Effect Upon Noise

required from the supply to charge the output capacitance will cause voltage variations at the ADC supply line. If

these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Similarly,

discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current

into the die substrate, causing "ground bounce" noise in the substrate that will degrade noise performance if that

current is large enough. The larger the output capacitance, the more current flows through the device power

supply line and die substrate and the greater is the noise coupled into the analog path.

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