GND

SAMPLING

CAPACITOR

SW1

-

+

CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

V

/2

DD

SW2

V

IN

GND

SAMPLING

CAPACITOR

SW1

-

+

CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

V

/2

DD

V

IN

ADCS7476, ADCS7477, ADCS7478

SNAS192F – APRIL 2003 – REVISED MARCH 2013

www.ti.com

APPLICATIONS INFORMATION

ADCS7476/77/78 OPERATION

The ADCS7476/77/78 are successive-approximation analog-to-digital converters designed around a charge-

redistribution digital-to-analog converter. Simplified schematics of the ADCS7476/77/78 in both track and hold

operation are shown in Figure 26 and Figure 27, respectively. In Figure 26 the device is in track mode: switch

SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in

this state until CS is brought low, at which point the device moves to hold mode.

Figure 27 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining

the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-

redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is

balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of

the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK.

Figure 26. ADCS7476/77/78 in Track Mode

Figure 27. ADCS7476/77/78 in Hold Mode

USING THE ADCS7476/77/78

Serial interface timing diagrams for the ADCS7476/77/78 are shown in Figure 3, Figure 4, and Figure 5. CS is

chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the

conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is

found.

Basic operation of the ADCS7476/77/78 begins with CS going low, which initiates a conversion process and data

transfer. Subsequent rising and falling edges of SCLK will be labeled with reference to the falling edge of CS; for

example, "the third falling edge of SCLK" shall refer to the third falling edge of SCLK after CS goes low.

At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold

mode. The input signal is sampled and held for conversion at the falling edge of CS. The converter moves from

hold mode to track mode on the 13th rising edge of SCLK (see Figure 3, Figure 4, or Figure 5). The SDATA pin

will be placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever

to begin another conversion.

16

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