PS20313

Table of Contents

Features ......................................................................................................................................................................1

Description ..................................................................................................................................................................1

Applications ................................................................................................................................................................1

Overview.......................................................................................................................................................................6

1

Application Diagram .............................................................................................................................................8

2

Functional Overview.............................................................................................................................................9

2.1

Introduction..................................................................................................................................................9

2.2

Analogue-to-Digital Converter .....................................................................................................................9

2.3

QPSK Demodulator.......................................................................................................................................9

2.4

Forward Error Correction ...........................................................................................................................10

2.4.1

Viterbi Error Count Measurement .....................................................................................................10

2.4.2

The Frame Alignment Block................................................................................................................12

2.4.3

The De-Interleaver Block ....................................................................................................................12

2.4.4

The Reed-Solomon Decoder Block .....................................................................................................14

2.4.5

The Energy Dispersal (de-scrambler) Block, DVB Only.......................................................................15

2.4.6

Output Stage.......................................................................................................................................15

2.5

Control........................................................................................................................................................15

2.5.1

Symbol Rate and Code Rate Search Mode .........................................................................................16

2.6

DiSEqC Transmit and Receive Messages ....................................................................................................16

2.6.1

DiSEqC Transmitting Messages ..........................................................................................................16

2.6.2

DiSEqC Receiving Messages................................................................................................................17

3

Microprocessor Control......................................................................................................................................17

3.1

RADD: 2-wire Register Address (W

) ...........................................................................................................17

3.2

Primary 2-wire Bus Interface......................................................................................................................18

3.3

Secondary 2-wire Bus for Tuner Control ....................................................................................................19

PLESSEY SEMICONDUCTORS LTD

TAMERTON ROAD | ROBOROUGH | PLYMOUTH | DEVON | PL6 7BQ

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