PS20313

Table of Figures

Figure 1 - Functional Block Diagram.............................................................................................................................1

Figure 2 - PS20313 Pin Allocation.................................................................................................................................2

Figure 3 - PS20313 Functional Block Diagram..............................................................................................................6

Figure 4 - Typical Application Schematic......................................................................................................................8

Figure 5 - Viterbi Block Diagram.................................................................................................................................10

Figure 6 - Viterbi Error Count Measurement .............................................................................................................11

Figure 7 - Viterbi Error Count Coarse Indication ........................................................................................................12

Figure 8 - DVB Conceptual Diagram of the Convolutional De-Interleaver Block .......................................................13

Figure 9 - DSS Conceptual Diagram of the Convolutional De-Interleaver Block ........................................................13

Figure 10 - DVB Block Structure .................................................................................................................................14

Figure 11 - DVB Energy Dispersal Conceptual Diagram..............................................................................................14

Figure 12 - DVB Energy Dispersal Conceptual Diagram..............................................................................................15

Figure 13 - PS20313 Control Structure.......................................................................................................................16

Figure 14 - Primary 2-Wire Bus Timing.......................................................................................................................20

Figure 15 - Crystal Oscillator Circuit ...........................................................................................................................21

Figure 16 - Package dimensions .................................................................................................................................25

Table of Tables

Table 1 - Primary 2-wire bus timing ...........................................................................................................................20

PLESSEY SEMICONDUCTORS LTD

TAMERTON ROAD | ROBOROUGH | PLYMOUTH | DEVON | PL6 7BQ

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