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ML610Q461 Datasheet(PDF) 28 Page - List of Unclassifed Manufacturers |
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ML610Q461 Datasheet(HTML) 28 Page - List of Unclassifed Manufacturers |
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28 / 34 page ![]() FEDL610Q461-01 ML610Q461/ML610Q462/ML610Q463 AC CHARACTERISTICS (Synchronous Serial Port) (VDD = 1.25 to 3.6V, VSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Parameter Symbol Condition Rating Unit Min. Typ. Max. SCLKn input cycle (slave mode) tSCYC When RC oscillation is 500kHz * 2 (V DD = 1.25 to 3.6V) 10 µs When RC oscillation is 2MHz * 3 (V DD = 1.8 to 3.6V) 2 SCLKn output cycle (master mode) tSCYC SCLKn* 1 s SCLKn input pulse width (slave mode) tSW When RC oscillation is 500kHz * 2 (V DD = 1.25 to 3.6V) 4 µs When RC oscillation is 2MHz * 3 (V DD = 1.8 to 3.6V) 04 SCLKn output pulse width (master mode) tSW SCLKn* 1 ×0.4 SCLKn* 1 ×0.5 SCLKn* 1 ×0.6 s SOUTn output delay time (slave mode) tSD When RC oscillation is 500kHz * 2 (V DD = 1.25 to 3.6V) output load 10pF 500 ns When RC oscillation is 2MHz * 3 (V DD = 1.8 to 3.6V) output load 10pF 240 SOUTn output delay time (master mode) tSD When RC oscillation is 500kHz * 2 (V DD = 1.25 to 3.6V) output load 10pF 500 ns When RC oscillation is 2MHz * 3 (V DD = 1.8 to 3.6V) output load 10pF 240 SINn input setup time (slave mode) tSS 80 ns SINn input setup time (master mode) tSS When RC oscillation is 500kHz * 2 (V DD = 1.25 to 3.6V) 500 ns When RC oscillation is 2MHz * 3 (V DD = 1.8 to 3.6V) 240 SINn input hold time tSH When RC oscillation is 500kHz * 2 (V DD = 1.25 to 3.6V) 300 ns When RC oscillation is 2MHz * 3 (V DD = 1.8 to 3.6V) 80 n= 0,1 *1: Clock period selected with SnCK3–0 of the serial port n mode register (SIOnMOD1) * 2: When 500kHz RC oscillation is selected by OSCM2 of the frequency control register (FCON0) * 3: When 2MHz RC oscillation is selected by OSCM2 of the frequency control register (FCON0) tSD SCLKn* SINn* SOUTn* *: Indicates the secondary function of the port (n= 0,1) tSD tSS tSH tSW tSW tSCYC 28/34 |
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