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ML610Q461 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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ML610Q461 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 34 page ![]() FEDL610Q461-01 ML610Q461/ML610Q462/ML610Q463 BLOCK DIAGRAM Block Diagram of ML610Q461/ML610Q462/ML610Q463 Figure 1 show the block diagram of the ML610Q461/ML610Q462/ML610Q463. “*” indicates the secondary or tertiary function of each port. Figure 1 ML610Q461/ML610Q462/ML610Q463 Block Diagram Program Memory (Flash) 16Kbyte RAM 1Kbyte Interrupt Controller CPU (nX-U8/100) Timing Controller EA SP On-Chip ICE Instruction Decoder BUS Controller Instruction Register TBC INT 4 INT 1 WDT INT 4 8bit Timer ×4 Capture ×2 GPIO INT 5 Data-bus TEST0 RESET_N OSC XT0 XT1 LSCLK* OUTCLK* Power VDDL LCD Driver LCD BIAS VL1, VL2, VL3 C1, C2 RC-ADC X2 CS0* IN0* RS0* RT0* CRT0* RCM* RESET & TEST ALU EPSW1~3 PSW ELR1~3 LR ECSR1~3 DSR/CSR PC GREG 0~15 VPP VDD VSS INT 1 Display register 96bit COM0 to COM3 SEG8 to SEG23 (ML610Q461) SEG8 to SEG27 (ML610Q462) SEG8 to SEG31 (ML610Q463) P00 to P04 P20 to P21 P30 to P35 P40 to P47 SSIO SCK0* SIN0* SOUT0* INT 1 UART INT 1 INT 1 PWM RXD0* TXD0* PWM0* TEST1_N P60 to P67 (ML610Q461) P60 to P63 (ML610Q462) CS1* IN1* RS1* RT1* 4/34 |
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