FEDL9212-01

LAPIS Semiconductor

ML9212

4/17

PIN DESCRIPTIONS

Symbol

Pin

Type

Description

43, 56

—

Power supply pins for VFD driver circuit.

43 pin and 56 pin should be connected externally.

14

—

Power supply pin for logic drive.

D-GND

12, 49

—

L-GND

21

—

D-GND is ground pin for the VFD driver circuit. L-GND is ground pin

for the logic circuit. 12 pin, 21 pin and 49 pin should be connected

externally.

SEG1 to 22

30 to 42,

44 to 48,

50 to 53

O

Segment (anode) signal output pins for a VFD tube.

These pins can be directly connected to the VFD tube.

External circuit is not required.

SEG23 to 32

1 to 8,

54, 55

O

Segment (anode) signal output pins for a VFD tube.

These pins can be directly connected to the VFD tube.

External circuit is not required.

GRID1 to 3

9, 10, 11

O

Inverted Grid signal output pins.

For pre-driver, the external circuit is required.

CS

18

I

Chip select input pin.

Data is not transferred when CS is set to a Low level.

CLOCK

19

I

Shift clock input pin.

Serial data shifts at the rising edge of the CLOCK.

DATA IN

20

I

Serial data input pin (positive logic).

Data is input to the shift register at the rising edge of the CLOCK

signal.

DUP/TRl

24

I

Duplex/Triplex operation select input pin.

Triplex (1/3 duty) operation is selected when this pin is set to L-GND.

M/S

25

I

Master/Slave mode select input pin.

Slave mode is selected when this pin is set to L-GND.

DIM IN

15

I

Dimming pulse input.

When the slave mode is selected, the pulse width of the all segment

output are controlled by a input pulse width of DIM IN.

Connect this pin to the master side DIM OUT pin at the slave mode.

When the master mode is selected, the input level of this pin is

ignored and the pulse width of the all grids and segment outputs are

controlled by a built-in 10-bit dimming circuit.