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WM1811A Datasheet(PDF) 110 Page - Wolfson Microelectronics plc

Part # WM1811A
Description  Multi-Channel Audio Hub CODEC for Smartphones
PDF  328 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 110 Page - Wolfson Microelectronics plc

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WM1811A
Production Data
w
PD, November 2013, Rev 4.1
110
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
5:0
MIXOUTR_VOL[5:0]
39h
(0dB)
MIXOUTRVOL (Right Mixer Output
PGA) Volume
-57dB to +6dB in 1dB steps
00_0000 = -57dB
00_0001 = -56dB
… (1dB steps)
11_1111 = +6dB
(See Table 64 for output PGA
volume control range)
Table 61 Mixer Output PGA (MIXOUTLVOL, MIXOUTRVOL) Control
The headphone output PGA controls are shown inTable 62.The HPOUT1_VU bits control the loading
of the headphone PGA volume data. When HPOUT1_VU is set to 0, the volume control data will be
loaded into the respective control register, but will not actually change the gain setting. The
headphone PGA volume settings are both updated when a 1 is written toeither HPOUT1_VU bit. This
makes it possible to update the gain of both output paths simultaneously.
The HPOUT1_ATTN register controls a -3dB attenuation function in the HPOUT1L and HPOUT1R
signal paths. (Note that this single register applies to the Left and Right output paths.) The output path
Signal to Noise Ratio (SNR) may be improved when the HPOUT1_ATTN bit is set, but the maximum
signal level is reduced by 3dB.
Note
that,
when
the
HPOUT1_ATTN
register
is
updated
in
Register
Control mode
(CP_DYN_PWR=0), the HPOUT1_ATTN function is not fully implemented until a ‘1’ has been written
to HPOUT1_VU. See “Charge Pump” for details of the CP_DYN_PWR register bit.
The DAC1L_TO_HPOUT1L and DAC1R_TO_HPOUT1R register bits allow the DACL and DACR
outputs to be selected as the single input to the HPOUT1L and HPOUT1R headphone output PGAs
respectively. When these bits are asserted, the respective output mixer settings are ignored, and only
the DAC path(s) are enabled. Note that these register controls are provided for software compatibility
with WM8994; it is not recommended to use these register bits.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R28 (001Ch)
Left Output
Volume
8
HPOUT1_VU
N/A
Headphone Output PGA Volume
Update
Writing a 1 to this bit will update
HPOUT1LVOL and HPOUT1RVOL
volumes simultaneously.
7
HPOUT1L_ZC
0
HPOUT1LVOL (Left Headphone
Output PGA) Zero Cross Enable
0 = Zero cross disabled
1 = Zero cross enabled
6
HPOUT1L_MUTE_
N
1
HPOUT1LVOL (Left Headphone
Output PGA) Mute
0 = Mute
1 = Un-mute
5:0
HPOUT1L_VOL[5:0
]
2Dh
(-12dB)
HPOUT1LVOL (Left Headphone
Output PGA) Volume
-57dB to +6dB in 1dB steps
00_0000 = -57dB
00_0001 = -56dB
… (1dB steps)
11_1111 = +6dB
(See Table 64 for output PGA
volume control range)



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